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Technical Committee on Reconfigurable Systems (RECONF) (Searched in: 2016)
Search Results: Keywords 'from:2016-09-05 to:2016-09-05'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF | 2016-09-05 13:10 |
Toyama | Univ. of Toyama | Functional Improvement of cReComp Design Tool for Software-Component Generation of FPGA Processing Kazushi Yamashina, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota (Utsunomiya Univ.)  RECONF2016-24 |
(To be available after the conference date) [more] | RECONF2016-24 pp.1-6 |
| RECONF | 2016-09-05 13:35 |
Toyama | Univ. of Toyama | RECONF2016-25 |
(To be available after the conference date) [more] | RECONF2016-25 pp.7-12 |
| RECONF | 2016-09-05 14:00 |
Toyama | Univ. of Toyama | [Short Paper]
Study and Evaluation of FPGA based I/O Accelerator for the Flash Storage Kazushi Nakagawa, Shotaro Shintani, Hirotoshi Akaike, Kentaro Shimada (Hitachi) RECONF2016-26 |
(To be available after the conference date) [more] | RECONF2016-26 pp.13-14 |
| RECONF | 2016-09-05 14:35 |
Toyama | Univ. of Toyama | The effect of the C ++ template meta-programming in high-level synthesis Kenichiro Mitsuda, Owada Hiroshi, Shinji Yamamoto (ISP) RECONF2016-27 |
In this talk, we introduce technique of high level synthesis using C++ template meta-programming. [more] | RECONF2016-27 pp.15-17 |
| RECONF | 2016-09-05 15:00 |
Toyama | Univ. of Toyama | RECONF2016-28 |
[more] | RECONF2016-28 pp.19-22 |
| RECONF | 2016-09-05 15:35 |
Toyama | Univ. of Toyama | Proposal of vertical stacked reconfigurable Fe-FET NAND logic and its application to combination logic, flip-flop and LUT Shigeyoshi Watanabe (Shonan Inst. of Tech.), Tomohiro Yokota (DNP Data Techno), Shoto Tamai (Oi Electric), Takumi Sato (Shonan Inst. of Tech.) RECONF2016-29 |
[more] | RECONF2016-29 pp.23-28 |
| RECONF | 2016-09-05 16:00 |
Toyama | Univ. of Toyama | Tomohiro Tanaka, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Takashi Ishiguro (Taiyo Yuden) RECONF2016-30 |
(To be available after the conference date) [more] | RECONF2016-30 pp.29-34 |
| RECONF | 2016-09-05 16:35 |
Toyama | Univ. of Toyama | [Invited Talk]
Verification and Debugging Support Techniques for High-Level Designs Takeshi Matsumoto (INCT) RECONF2016-31 |
[more] | RECONF2016-31 p.35 |
| RECONF | 2016-09-06 09:10 |
Toyama | Univ. of Toyama | [Invited Talk]
Accelerating an IoT Application by using CPU-FPGA tightly coupled architecture Yuki Kobayashi, Yoshikazu Watanabe, Seiya Shibata, Takashi Takenaka, Takeo Hosomi, Yuichi Nakamura (NEC) RECONF2016-32 |
CPU-FPGA tightly coupled architecture is an emerging architecture where FPGA is tightly coupled with CPU. We introduce a... [more] | RECONF2016-32 p.37 |
| RECONF | 2016-09-06 10:30 |
Toyama | Univ. of Toyama | Concept of PC-FPGA Hybrid Cluster system by General-purpose FPGA board Keisuke Takano, Akira Uejima, Ryo Ozaki, Masaki Kohata (Okayama Univ. of Science) RECONF2016-33 |
Parallel processing by PC cluster and hardware acceleration by FPGA are useful technologies in a field of high performan... [more] | RECONF2016-33 pp.39-44 |
| RECONF | 2016-09-06 10:55 |
Toyama | Univ. of Toyama | A Study of Methodology and Tools for Open-source FPGA Accelerators Takuya Nakamichi, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2016-34 |
Today's information and communication society requires more and higher-performance computing devices with the constraint... [more] | RECONF2016-34 pp.45-50 |
| RECONF | 2016-09-06 11:20 |
Toyama | Univ. of Toyama | RECONF2016-35 |
(To be available after the conference date) [more] | RECONF2016-35 pp.51-56 |
| RECONF | 2016-09-06 13:00 |
Toyama | Univ. of Toyama | A Memory-based Accelerator for a Random Forest Classification using Altera SDK for OpenCL Hiroki Nakahara, Akira Jinguji, Tomoya Fujii, Shinpei Sato (TITECH), Naoya Maruyama (RIKEN) RECONF2016-36 |
[more] | RECONF2016-36 pp.57-62 |
| RECONF | 2016-09-06 13:25 |
Toyama | Univ. of Toyama | A Memory Based Realization of the Binarized Deep Convolutional Neural Network Hiroki Nakahara, Haruyoshi Yonekawa (TITECH), Tsutomu Sasao (Meiji Univ.), Hisashi Iwamoto (Poco a poco Networks), Masato Motomura (Hokkaido Univ.) RECONF2016-37 |
[more] | RECONF2016-37 pp.63-68 |
| RECONF | 2016-09-06 13:50 |
Toyama | Univ. of Toyama | An Efficient and Small-Scaled RNN Hardware Architecture Based on Approximation of RNN Algorithm for Hardware Implementation Daichi Murata, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ.) RECONF2016-38 |
This paper presents an efficient and small-scaled RNN (Recurrent Neural Network) hardware architecture based on approxim... [more] | RECONF2016-38 pp.69-74 |
| RECONF | 2016-09-06 14:15 |
Toyama | Univ. of Toyama | RECONF2016-39 |
[more] | RECONF2016-39 pp.75-80 |
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