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Technical Committee on Reconfigurable Systems (RECONF) (Searched in: 2015)
Search Results: Keywords 'from:2015-06-19 to:2015-06-19'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF | 2015-06-20 13:35 |
Kyoto | Kyoto University | Real Chip evaluation of a dynamically reconfigurable processor MuCCRA-4 with ST micro 28nm Process Hideharu Amano, Toru Katagiri (Keio Univ.)  RECONF2015-21 |
[more] | RECONF2015-21 pp.113-118 |
| RECONF | 2015-06-20 14:00 |
Kyoto | Kyoto University | On the Evaluation Board AISTino equipped with the Fourth Flex Power FPGA chip with SOTB transistors Hanpei Koike, Masakazu Hioki, Yasuhiro Ogasahara (AIST), Hayato Ishigaki, Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa (AIST) RECONF2015-22 |
Flex Power FPGA utilizes threshold voltage programmability to reduce its static power by the body bias control of circui... [more] | RECONF2015-22 pp.119-124 |
| RECONF | 2015-06-20 14:25 |
Kyoto | Kyoto University | Tile-base PLA Cell with Uni-Switch Structure Atsushi Nanri, Kosuke Murakami, Daijiro Murooka, Takuya Hirata, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu) RECONF2015-23 |
[more] | RECONF2015-23 pp.125-130 |
| RECONF | 2015-06-20 14:50 |
Kyoto | Kyoto University | High-speed scrubbing on optically reconfigurable gate array Takumi Fujimori, Minoru Watanabe (Shizuoka Univ.) RECONF2015-24 |
[more] | RECONF2015-24 pp.131-134 |
| RECONF | 2015-06-20 15:25 |
Kyoto | Kyoto University | Consideration of a reconfigurable device MPLD constructed with MLUTs that equips a crossbar switch Naoya Tokusada, Tetsuo Hironaka, Kazuya Tanigawa (HCU), Takashi Ishiguro (Taiyo Yuden) RECONF2015-25 |
[more] | RECONF2015-25 pp.135-140 |
| RECONF | 2015-06-20 15:50 |
Kyoto | Kyoto University | An Online Task Placement Algorithm Based on MER Enumeration for Partially Reconfigurable Device Tieyuan Pan, Zhu Li, Lian Zeng, Takahiro Watanabe (Waseda Univ.), Yasuhiro Takashima (Univ. of Kitakyushu) RECONF2015-26 |
Recently, due to the development of technology, the embedded application becomes more and more complex. Consequently, no... [more] | RECONF2015-26 pp.141-146 |
| RECONF | 2015-06-20 16:15 |
Kyoto | Kyoto University | A Technology Mapping Method for Scalable Logic Module Ryo Araki, Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ) RECONF2015-27 |
In order to implement logic functions, conventional field-programmable gate arrays (FPGAs) employs look-up tables (LUTs)... [more] | RECONF2015-27 pp.147-152 |
| RECONF | 2015-06-20 16:40 |
Kyoto | Kyoto University | Data-Triggered Breakpoint for In-Circuit Debug without Re-implementation Yutaka Tamiya, Yoshinori Tomita, Toshiyuki Ichiba, Kaoru Kawamura (Fujitsu Labs.) RECONF2015-28 |
(To be available after the conference date) [more] | RECONF2015-28 pp.153-158 |
| RECONF | 2015-06-20 17:15 |
Kyoto | Kyoto University | High-Level Synthesis Compiler for Hierarchical and Modular Design of Stream Computing Cores Kentaro Sano, Ryo Ito, Keisuke Sugawara, Satoru Yamamoto (Tohoku Univ.) RECONF2015-29 |
Although FPGA-based custom hardware is expected for low-power and high-performance computation, productivity improvement... [more] | RECONF2015-29 pp.159-164 |
| RECONF | 2015-06-20 17:40 |
Kyoto | Kyoto University | An Implementation and Evaluation of A Generic Interface between PC and FPGA with AHCI Takefumi Miyoshi, Satoshi Funada (e-trees) RECONF2015-30 |
[more] | RECONF2015-30 pp.165-170 |
| RECONF | 2015-06-20 18:05 |
Kyoto | Kyoto University | FPGA design using high-level description
-- sound synthesizer implementation and its evaluation -- Fang-Xiang Gao, Yoshiki Yamaguchi, Yuetsu Kodama (Univ. Tsukuba) RECONF2015-31 |
(To be available after the conference date) [more] | RECONF2015-31 pp.171-176 |
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