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Technical Committee on Reconfigurable Systems (RECONF)  (2014)

Chair: Kentaro Sano (RIKEN)
Vice Chair: Yoshiki Yamaguchi (Tsukuba Univ.), Tomonori Izumi (Ritsumeikan Univ.)
Secretary: Yuuki Kobayashi (NEC), Hiroki Nakahara (Tokyo Inst. of Tech.)
Assistant: Yukitaka Takemura (INTEL), Yasunori Osana (Ryukyu Univ.)

Search Results: Keywords 'from:2015-01-29 to:2015-01-29'

[Go to Official RECONF Homepage (Japanese)] 
Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Ascending)
 Results 21 - 40 of 40 [Previous]  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
09:10
Kanagawa Hiyoshi Campus, Keio University Intrusion Detection in High-Speed Networks with a Multi-Byte Transition NFA
Shin'ichi Wakabayashi, Tomoaki Hashimoto, Ryohei Koishi, Hiroki Takaguchi, Shinobu Nagayama, Masato Inagi (Hiroshima City Univ.) VLD2014-133 CPSY2014-142 RECONF2014-66
 [more] VLD2014-133 CPSY2014-142 RECONF2014-66
pp.133-138
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
09:30
Kanagawa Hiyoshi Campus, Keio University Implementation and Evaluation of the Low-level Communication Mechanism on FLOPS-2D
Katsuki Kyan, Makoto Arakaki, Yusuke Hirai, Hiroki Nakasone (Univ. of the Ryukyus), Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.), Yasunori Osana (Univ. of the Ryukyus) VLD2014-134 CPSY2014-143 RECONF2014-67
FLOPS-2D is a multiple-FPGA computer system that consists of several FLOPS boards. Each FLOPS board has one FPGA, memory... [more] VLD2014-134 CPSY2014-143 RECONF2014-67
pp.139-143
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
09:50
Kanagawa Hiyoshi Campus, Keio University A feasibility study on implementing numerical applications on FPGAs using Vivado HLS
Hiroki Nakasone, Yasunori Osana, Yasunori Nagata (Univ of Ryukyu) VLD2014-135 CPSY2014-144 RECONF2014-68
FPGAs are one of hopeful candidate of accelerator for scientific computing in near future. There are many attempts in va... [more] VLD2014-135 CPSY2014-144 RECONF2014-68
pp.145-150
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
10:30
Kanagawa Hiyoshi Campus, Keio University Error detection using residue signed-digit number arithmetic for arithmetic circuits
Yoshitomo Nema, Yuuki Tanaka, Kazuhiro Motegi, Shugang Wei (Gunma Univ) VLD2014-136 CPSY2014-145 RECONF2014-69
For error detection of multiply-accumulate operation, a residue error detector can be considered for the VLSI implementa... [more] VLD2014-136 CPSY2014-145 RECONF2014-69
pp.151-156
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
10:50
Kanagawa Hiyoshi Campus, Keio University A Hardware Trojan Detection Method based on Trojan net features
Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-137 CPSY2014-146 RECONF2014-70
Recently, digital ICs are designed by outside vendors to reduce costs
in semiconductor industry. This circumstance intr... [more]
VLD2014-137 CPSY2014-146 RECONF2014-70
pp.157-162
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
11:10
Kanagawa Hiyoshi Campus, Keio University The proposal of the convex area maze router on LSI design automation
Yohei Horino, Jun Hirayama, Yukiko Ohishi, Toshiyuki Tsutsumi (Meiji Univ.) VLD2014-138 CPSY2014-147 RECONF2014-71
We developed the convex area maze router that extends the channel intersection maze router as a high-speed routing algor... [more] VLD2014-138 CPSY2014-147 RECONF2014-71
pp.163-168
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
11:30
Kanagawa Hiyoshi Campus, Keio University Detecting Missed Arithmetic Optimization Opportunities Using Random Testing of C Compilers
Atsushi Hashimoto, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2014-139 CPSY2014-148 RECONF2014-72
This article presents new methods of detecting missed arithmetic optimization opportunities of C compilers by random tes... [more] VLD2014-139 CPSY2014-148 RECONF2014-72
pp.169-174
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
11:50
Kanagawa Hiyoshi Campus, Keio University An FPGA Implementation of Deep Convolutional Neural Network using Synchronous Shift Data Transfer
Li Ning, Yoichi Tomioka, Hitoshi Kitazawa (TUAT) VLD2014-140 CPSY2014-149 RECONF2014-73
Due to its effectiveness, machine learning based on deep neural network is getting more and more popular in image and sp... [more] VLD2014-140 CPSY2014-149 RECONF2014-73
pp.175-180
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
13:20
Kanagawa Hiyoshi Campus, Keio University Implementation of Sparse Matrix-Vector Multiplication on GPU and Its Application to the Conjugate Gradient Method
Shotaro Asano, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.) VLD2014-141 CPSY2014-150 RECONF2014-74
Numerical simulations are offten performed by converting complex partial differential equations into a system of discret... [more] VLD2014-141 CPSY2014-150 RECONF2014-74
pp.181-186
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
13:40
Kanagawa Hiyoshi Campus, Keio University Relaxing constraint conditions in parallelizing compiler based on a polyhedral model
Toma Ogata, Hidehiro Nakano, Arata Miyauchi (Tokyo City Univ.) VLD2014-142 CPSY2014-151 RECONF2014-75
Recently, it is general that computer has more than one processor inside and it is important to parallelize program to ... [more] VLD2014-142 CPSY2014-151 RECONF2014-75
pp.187-192
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
14:00
Kanagawa Hiyoshi Campus, Keio University Acceleration of Big Data Partitioning with Multiple FPGA boards
Ryu Kudo, Saori Sudo, Yasin Oge (UEC), Yuta Terada (AVAL DATA), Masato Yoshimi, Hidetsugu Irie, Tsutomu Yoshinaga (UEC) VLD2014-143 CPSY2014-152 RECONF2014-76
Data volume and diversity that we treat have been increasing rapidly because of increasing popularity of the internet an... [more] VLD2014-143 CPSY2014-152 RECONF2014-76
pp.193-198
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
14:20
Kanagawa Hiyoshi Campus, Keio University Reliability Management in 2-layered Supervisor Processor
Daiki Yamamoto, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ) VLD2014-144 CPSY2014-153 RECONF2014-77
Computer systems are not only used in consumer electronics such as mobile phones and televisions but various industria... [more] VLD2014-144 CPSY2014-153 RECONF2014-77
pp.199-204
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
14:55
Kanagawa Hiyoshi Campus, Keio University Design and Implementation of Portable and High-speed FPGA Accelerator employing USB3.0
Takuma Usui, Ryohei Kobayashi, Kenji Kise (Tokyo Tech) VLD2014-145 CPSY2014-154 RECONF2014-78
FPGA accelerators can obtain higher computation performance and better power efficiency than CPUs and GPUs, because desi... [more] VLD2014-145 CPSY2014-154 RECONF2014-78
pp.205-210
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
15:15
Kanagawa Hiyoshi Campus, Keio University MieruSys Project : Developing an Advanced Computer System with Multiple FPGAs
Yuki Matsuda, Eri Ogawa, Tomohiro Misono (Tokyo Tech), Naoki Fujieda, Shuichi Ichikawa (TUT), Kenji Kise (Tokyo Tech) VLD2014-146 CPSY2014-155 RECONF2014-79
This paper describes the design and current development of MieruSys project which develops a future computer system with... [more] VLD2014-146 CPSY2014-155 RECONF2014-79
pp.211-216
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
15:35
Kanagawa Hiyoshi Campus, Keio University FPGA Vendor Independent Descriptions and Designs of Synchronous FIFOs
Tomonori Izumi (Ritsumeikan Univ.) VLD2014-147 CPSY2014-156 RECONF2014-80
 [more] VLD2014-147 CPSY2014-156 RECONF2014-80
pp.217-220
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
15:55
Kanagawa Hiyoshi Campus, Keio University Obfuscated Hardware Implementation of PLC Instructions with Opaque Predicates
Kazuki Uyama, Naoki Fujieda, Shuichi Ichikawa (Toyohashi Tech.) VLD2014-148 CPSY2014-157 RECONF2014-81
Tamper-proofing technology for instruction sequences of programmable logic controllers(PLCs)is required to protect trade... [more] VLD2014-148 CPSY2014-157 RECONF2014-81
pp.221-226
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
16:30
Kanagawa Hiyoshi Campus, Keio University A Low Latency Real-Time Execution on Dependable Responsive Multithreaded Processor
Keigo Mizotani, Yusuke Hatori, Yusuke Kumura, Masayoshi Takasu, Hiroyuki Chishiro, Nobuyuki Yamasaki (Keio Univ.) VLD2014-149 CPSY2014-158 RECONF2014-82
In recent embedded real-time systems, there are many systems with both hard real-time tasks and soft real-time tasks. Wh... [more] VLD2014-149 CPSY2014-158 RECONF2014-82
pp.227-232
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
16:50
Kanagawa Hiyoshi Campus, Keio University A Latency-Aware Packet Scheduling on Responsive Link
Kouhei Oosawa, Shuma Hagiwara, Yusuke Kumura, Keigo Mizotani, Masayoshi Takasu, Nobuyuki Yamasaki (Keio Univ.) VLD2014-150 CPSY2014-159 RECONF2014-83
Recently, distributed systems with multiple processors are now quite widespread. In particular, distributed systems with... [more] VLD2014-150 CPSY2014-159 RECONF2014-83
pp.233-238
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
17:10
Kanagawa Hiyoshi Campus, Keio University Real-time contour extraction for moving objects directly operating MPEG encoded data
Syosuke Maruyama, Hidehiro Nakano, Arata Miyauchi (Tokyo City Univ.) VLD2014-151 CPSY2014-160 RECONF2014-84
Recently, the use of multimedia resources has spread, extensively.
Especially, MPEG video has been used in the various... [more]
VLD2014-151 CPSY2014-160 RECONF2014-84
pp.239-244
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
17:30
Kanagawa Hiyoshi Campus, Keio University A Cache to Cache Communication Strategy for Wireless 3D Multi-Core Processors
Masataka Matsumura (UEC), Masaaki Kondo (Univ. Tokyo), Hiroki Matsutani (Keio Univ.), Yasutaka Wada (Waseda Univ.), Hiroki Honda (UEC) VLD2014-152 CPSY2014-161 RECONF2014-85
The inductive-coupling 3D chip stacking technique has several advantages over TSV-based 3D stacking. For example, its ma... [more] VLD2014-152 CPSY2014-161 RECONF2014-85
pp.245-250
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