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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| NLP, MSS | 2024-03-14 16:05 |
Misc. | Kikai-Shinko-Kaikan Bldg. | Functional electrical stimulator with wireless sequential logic central pattern generator model Rikuto Nozu, Hiroyuki Torikai (Hosei Univ)  MSS2023-97 NLP2023-149 |
In this study, we design a functional electrical stimulator using a wireless sequential logic circuit central pattern ge... [more] | MSS2023-97 NLP2023-149 p.123 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2023-11-15 14:40 |
Kumamoto | Civic Auditorium Sears Home Yume Hall (Primary: On-site, Secondary: Online) |
A 183.4 nJ/inference 152.8 µW Single-Chip Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application Rei Sumikawa, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda (UTokyo) VLD2023-39 ICD2023-47 DC2023-46 RECONF2023-42 |
A 183.4-nJ/inference single-chip wired-logic DNN processor that is capable of recognizing all 35 commands defined in the... [more] | VLD2023-39 ICD2023-47 DC2023-46 RECONF2023-42 pp.54-59 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2023-11-17 14:10 |
Kumamoto | Civic Auditorium Sears Home Yume Hall (Primary: On-site, Secondary: Online) |
Configuration Data Compression for SLM Fine-grained Reconfigurable Logic Souhei Takagi, Takuya Kozima, Hideharu Amano (Keio Univ), Morihiro Kuga, Masahiro Iida (Kumamoto Univ) VLD2023-72 ICD2023-80 DC2023-79 RECONF2023-75 |
SLM (Scalable Logic Module) is a fine-grained reconfigurable logic developed by Kumamoto University, characterized by it... [more] | VLD2023-72 ICD2023-80 DC2023-79 RECONF2023-75 pp.215-220 |
| CCS | 2023-11-11 13:30 |
Toyama | Toyama Prefectural University | Evaluation of a Small Signal Detection Circuit for Artificial Action Potentials in an Alginate Gel Membrane Soichiro Yamakawa, Kota Ando, Tetsuya Asai (Hokkaido Univ.) CCS2023-26 |
In recently years, AI has been applied to a wide range of applications, and the concept of having the human brain itself... [more] | CCS2023-26 pp.7-12 |
| PN | 2023-08-30 11:40 |
Hokkaido | (Primary: On-site, Secondary: Online) |
Reconfigurable All-Optical Logic Gate Using Quantum Dot Semiconductor Optical Amplifiers Taishi Takemoto, Yusuke Hatano, Motoharu Matsuura (UEC) PN2023-35 |
Recently, communication traffic has been increasing year by year, and the delay due to electrical signal processing in o... [more] | PN2023-35 pp.97-100 |
| SCE | 2023-08-08 11:25 |
Kanagawa | Yokohama National Univ. (Primary: On-site, Secondary: Online) |
Low-Cost Sorting Network Circuits Based on Temporal Logic Using Single Flux Quantum Circuits Zeyu Han, Zongyuan Li, Yamanashi Yuki, Yoshikawa Nobuyuki (YNU) SCE2023-5 |
Sorting is important in various applications such as image processing and switching systems. Hardware cost and power con... [more] | SCE2023-5 pp.22-27 |
| SCE | 2023-08-08 13:50 |
Kanagawa | Yokohama National Univ. (Primary: On-site, Secondary: Online) |
Design of an rf-SQUID with π-Josephson junction for inverter function of directly coupled quantum-flux-parametron logic Wataru Komiya, Naoki Takeuchi, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama National Univ.) SCE2023-8 |
Adiabatic quantum-flux-parametron (AQFP) logic relies on magnetic transformer for propagation and inversion, which prese... [more] | SCE2023-8 pp.39-44 |
| SCE | 2023-08-08 15:15 |
Kanagawa | Yokohama National Univ. (Primary: On-site, Secondary: Online) |
Design and Implementation of Neuron Circuit Using Adiabatic Quantum-Flux-Parametron Logic Tomoharu Yamauchi, Hao San (Tokyo City Univ.), Naoki Takeuchi (AIST/Yokohama National Univ.), Nobuyuki Yoshikawa (Yokohama National Univ.), Olivia Chen (Tokyo City Univ.) SCE2023-11 |
Adiabatic quantum-flux-parametron (AQFP) logic is a promising technology for future energy-efficient，high performance in... [more] | SCE2023-11 pp.53-57 |
| CCS, NLP | 2023-06-08 15:35 |
Tokyo | Tokyo City Univ. | A place and route method in AQFP circuits using multi-objective optimization Syota Kasai, Hidehiro Nakano (Tokyo City Univ.) NLP2023-18 CCS2023-6 |
In recent years, research has been conducted on AQFP circuits, which are superconducting logic circuits that consume les... [more] | NLP2023-18 CCS2023-6 pp.21-24 |
| HWS, VLD | 2023-03-02 13:50 |
Okinawa | (Primary: On-site, Secondary: Online) |
[Memorial Lecture]
CNFET7: An Open Source Cell Library for 7-nm CNFET Technology Chenlin Shi, Shinobu Miwa (UEC), Tongxin Yang, Ryota Shioya (UOT), Hayato Yamaki, Hiroki Honda (UEC) VLD2022-92 HWS2022-63 |
In this paper, we propose CNFET7, the first open-source cell library for7-nm carbon nanotube field-effect transistor (CN... [more] | VLD2022-92 HWS2022-63 p.110 |
| HWS, VLD | 2023-03-03 13:50 |
Okinawa | (Primary: On-site, Secondary: Online) |
A Logic Locking Method based on Function Modification Circuit Yohei Noguchi, Masayoshi Yoshimura (Kyoto Sangyo Univ.), Rei Miura, Toshinori Hosokawa (Nihon Univ.) VLD2022-107 HWS2022-78 |
In recent years, with the increase of VLSI integration, semiconductor design companies to design a VLSI have tended to u... [more] | VLD2022-107 HWS2022-78 pp.185-190 |
| SCE | 2023-01-20 13:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. (Primary: On-site, Secondary: Online) |
Design and Implementation of Power Consumption Reduction Binary Neural Networks Using Adiabatic Quantum-Flux-Parametron Logic Tomoharu Yamauchi, Hao San (Tokyo City Univ.), Nobuyuki Yoshikawa (Yokohama National Univ.), Olivia Chen (Tokyo City Univ.) SCE2022-14 |
Adiabatic quantum-flux-parametron (AQFP) logic is a promising technology for future energy-efficient，high performance in... [more] | SCE2022-14 pp.6-11 |
| SCE | 2023-01-20 14:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. (Primary: On-site, Secondary: Online) |
Introduction of a fluctuation mechanism of the oscillation frequency of the oscillator-based random number generator using Josephson oscillation Takeshi Onomi (Fukuoka Inst. Tech.) SCE2022-15 |
An oscillator-based true random number generator using superconducting single flux quantum circuits and Josephson oscill... [more] | SCE2022-15 pp.12-16 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2022-11-30 10:45 |
Kumamoto | (Primary: On-site, Secondary: Online) |
Prototype and evaluation of 4-input variable logic circuit with FGC using neuron CMOS inverter Shoma Ito, Daishi Nishiguchi, Masaaki Fukuhara (Tokai Univ.) VLD2022-45 ICD2022-62 DC2022-61 RECONF2022-68 |
Logic elements of FPGA generally use Look-Up Table (LUT) circuits, and the most common types of LUT are 4-input and 6-in... [more] | VLD2022-45 ICD2022-62 DC2022-61 RECONF2022-68 pp.150-155 |
| HWS, ICD | 2022-10-25 10:00 |
Shiga | (Primary: On-site, Secondary: Online) |
Hardware Evaluation of Romulus with Threshold Implementation and Its Simulation-Based Leakage Assessment Masaya Nemoto, Tamon Asano, Takeshi Sugawara (UEC) HWS2022-30 ICD2022-22 |
This paper provides a third-party hardware performance evaluation of the NIST LWC finalist Romulus with threshold imple... [more] |
HWS2022-30 ICD2022-22 pp.1-5 |
| ET | 2022-09-17 14:55 |
Hiroshima | Hiroshima University and Online (Primary: On-site, Secondary: Online) |
Proposal of Generating Propositional Logic Formulas Methods for Learning Support Systems of Intellectual Property Law Akihisa Tomita, Toru Kano, Takako Akakura (TUS) ET2022-18 |
The development and spread of information technology, called the 4th Industrial Revolution, has increased the value of i... [more] | ET2022-18 pp.48-51 |
| NC, IBISML, IPSJ-BIO, IPSJ-MPS [detail] | 2022-06-29 14:20 |
Okinawa | (Primary: On-site, Secondary: Online) |
LSI implementation of analog CMOS majority circuit for neural network applications Satoshi Ono, Satoshi Moriya, Yuka Kanke, Hideaki Yamamoto (Tohoku Univ.), Yasushi Yuminaka (Gunma Univ.), Shigeo Sato (Tohoku Univ.) NC2022-27 IBISML2022-27 |
Majority logic circuit is a circuit whose output is the majority value of multiple binary inputs. It can be applied to b... [more] | NC2022-27 IBISML2022-27 pp.189-192 |
| EMD | 2022-03-04 13:45 |
Online | Online | A Study on Sensorless Drive Methods for Brushless DC Motors Yuuki Harigaya, Kiyoshi Yoshida (NIT) EMD2021-17 |
The three-phase brushless DC motor uses a Hall sensor to detect the position of the magnetic poles of the rotor. Howeve... [more] | EMD2021-17 pp.13-18 |
| DC | 2022-03-01 10:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. (Primary: On-site, Secondary: Online) |
On Correction for Temperature and Voltage Effects in On-Chip Delay Measurement Takaaki Kato (KIT), Yousuke Miyake (PRIVATECH), Seiji Kajihara (KIT) DC2021-67 |
It is effective for aging of a logic circuit to measure a circuit delay periodically in field. In order to compare the d... [more] | DC2021-67 pp.18-23 |
| DC | 2022-03-01 13:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. (Primary: On-site, Secondary: Online) |
A Logic Locking Method based on SFLL-hd at Register Transfer Level Yohei Noguchi, Masayoshi Yoshimura (Kyoto Sangyo Univ.), Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.) DC2021-72 |
In recent years, with the increase of VLSI integration, LSI design companies utilize circuit design information, called ... [more] | DC2021-72 pp.45-50 |
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