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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 09:20 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A Handshake-delay-aware Scheduling Algorithm in High-level Synthesis for Four-phase Dual-rail Asynchronous Systems Kohta Itani, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)  VLD2015-60 DC2015-56 |
This report is intended to discuss the scheduling problem in high-level synthesis~(HLS) for four-phase dual-rail asynchr... [more] | VLD2015-60 DC2015-56 pp.147-152 |
| MW | 2014-12-19 11:15 |
Tokyo | Aoyama Gakuin Univ. Aoyama Campus | Design of Ultra Wide-Band Bandpass Filters Using Short-Circuited Stubs Ryuhi Hamano, Zhewang Ma, Masataka Ohira (Saitama Univ.), Chun-Ping Chen, Tetsuo Anada (Kanagawa Univ.) MW2014-171 |
In this paper, a novel synthesis theory of bandpass filters using short-circuited stubs is proposed. First, the variati... [more] | MW2014-171 pp.125-131 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 10:05 |
Oita | B-ConPlaza | Optimization for gate-level pipelined self-synchrnous circuit Atsushi Ito, Makoto Ikeda (Univ. of Tokyo) VLD2014-107 DC2014-61 |
With the down-scaling, circuit which has higher robustness is demanded. Dual-pipeline self synchronous circuit have inhe... [more] | VLD2014-107 DC2014-61 pp.233-238 |
| ISEC | 2014-09-05 15:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | GPU implementation of Ciphers using Schematic to Program Translator(SPT) Masashi Watanabe, Keisuke Iwai, Hidema Tanaka, Takakazu Kurokawa (NDA) ISEC2014-52 |
With the spread of heterogeneous computing, accelerators such as GPU are widely used. However, it is not easy to develop... [more] | ISEC2014-52 pp.35-42 |
| CPSY, DC (Joint) |
2014-07-29 09:00 |
Niigata | Toki Messe, Niigata | Verification Method of the Split Circuit by High-Level Synthesis Tool in a Circuit Partitioning mechanism Kazuya Matsuda (TAT), Takefumi Miyoshi (e-trees.Japan), Masashi Takemoto (TAT), Satoshi Funada (e-trees.Japan), Hironori Nakajo (TAT) CPSY2014-17 |
In recent years, a high-level synthesis tool has been attracted in designing hardware circuits instead of traditional HD... [more] | CPSY2014-17 pp.43-48 |
| CPSY, DC (Joint) |
2014-07-29 17:50 |
Niigata | Toki Messe, Niigata | Development of Cipher implementation tool using GUI Masashi Watanabe, Keisuke Iwai, Hidema Tanaka, Takakazu Kurokawa (NDA) CPSY2014-31 |
With the spread of heterogeneous computing, accelerators such as GPU are widely used. However, it is not easy to write ... [more] |
CPSY2014-31 pp.125-129 |
| CAS, SIP, MSS, VLD, SIS [detail] | 2014-07-11 15:10 |
Hokkaido | Hokkaido University | A distributed asynchronous arbiter for ring segmented bus type GALS systems Yoshiki Odagiri, Masaki Akari (Okayama Prefectural Univ.), Masafumi Kondo (Kawasaki Univ. of Medical Welfare), Tomoyuki Yokogawa, Yoichiro Sato, Kazutami Arimoto (Okayama Prefectural Univ.) CAS2014-44 VLD2014-53 SIP2014-65 MSS2014-44 SIS2014-44 |
A ring segmented bus (RSB) which connects the divided annular bus dynamically has been proposed for GALS systems. Howeve... [more] | CAS2014-44 VLD2014-53 SIP2014-65 MSS2014-44 SIS2014-44 pp.237-242 |
| VLD, IPSJ-SLDM | 2014-05-29 11:05 |
Fukuoka | Kitakyushu International Conference Center | Proposal of a Synthesis Flow for Asynchronous Circuits with Bundled-Data Implementation from a SystemC Model Taichi Komine, Hiroshi Saito (Univ. of Aizu) VLD2014-5 |
This paper proposes a synthesis flow for asynchronous circuits with bundled-data implementation from a SystemC model to ... [more] | VLD2014-5 pp.21-26 |
| MW | 2014-05-22 11:15 |
Kyoto | Doshisha Univ. | A Generation Technique of Transmission Zeros for Multimode Bandpass Filter Using Direct S/L Coupling Produced by Antiparallel Coupling Structure Masataka Ohira, Zhewang Ma (Saitama Univ.) MW2014-28 |
According to a general filter synthesis theory, the number of transmission zeros (TZs) that can be generated by a couple... [more] | MW2014-28 pp.25-30 |
| CPSY, DC | 2014-04-25 14:00 |
Tokyo | Construction of Design Environment for Asynchronous Circuits using DDL Cell Library Masashi Imai, Hiromasa Igarashi, Sanshiro Kudo (Hirosaki Univ.) CPSY2014-2 DC2014-2 |
As the VLSI fabrication technology advances, delay variations due to random process variations, crosstalk, and aging eff... [more] | CPSY2014-2 DC2014-2 pp.3-8 |
|
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-28 11:40 |
Kanagawa | Hiyoshi Campus, Keio University | Reduction Method of Asynchronous Circuits with Maximum Delay Loops using SDI Delay Assumption Tomoya Tasaki, Hiroto Kagotani, Yuji Sugiyama (Okayama Univ.) VLD2013-109 CPSY2013-80 RECONF2013-63 |
As one of the design methods of asynchronous pipeline circuits, a synthesis algorithm using dependency graphs has been p... [more] | VLD2013-109 CPSY2013-80 RECONF2013-63 pp.43-48 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-29 10:30 |
Kagoshima | A circuit division method for High-Level synthesis on Multi-FPGA systems in stream processing Daiki Kugami, Takaaki Miyajima, Hideharu Amano (Keio Univ.) CPSY2013-68 |
High-Level Synthesis (HLS) has been utilized as a practical tool especially for designing Field Programmable Gate Array... [more] |
CPSY2013-68 pp.53-58 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 10:55 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A Behavioral Synthesis Method for Asynchronous Pipelined Circuits with Bundled-data Implementation Naohiro Hamada, Hiroshi Saito (The Univ. of Aizu) VLD2012-77 DC2012-43 |
In this paper, we propose behavioral synthesis methods for asynchronous pipelined circuits with bundled-data implementat... [more] | VLD2012-77 DC2012-43 pp.105-110 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 10:55 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | Rational Function Approximation Using Vector Fitting and Equivalent Circuit Synthesis of Transmission Line Characteristics Daisuke Honda, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.) VLD2012-92 DC2012-58 |
This report describes the way how to approximate the frequency response of a transmission line by using a rational funct... [more] | VLD2012-92 DC2012-58 pp.189-194 |
| DC, CPSY (Joint) |
2012-08-03 09:00 |
Tottori | Torigin Bunka Kaikan | Implementation of the circuit division for High-Level Synthesis Daiki Kugami, Takaaki Miyajima, Hideharu Amano (Keio Univ.) CPSY2012-18 |
High-Level Synthesis has been researched and developed for these 20 years. Not only ASIC, but also reconfigurable devic... [more] |
CPSY2012-18 pp.55-60 |
| SCE | 2012-01-26 13:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. B3-2 | [Invited Talk]
Voltage waveform synthesizer based on SFQ pulse frequency modulation Keisuke Kuroiwa, Masataka Moriya, Hiroshi Shimada, Yoshinao Mizugaki (UEC), Masaaki Maezawa (AIST) SCE2011-22 |
A digital-to-analog converter based on single flux quantum (SFQ) circuits (RSFQ-DAC) is a candidate for ac voltage stand... [more] | SCE2011-22 pp.17-22 |
| IT | 2011-09-30 14:05 |
Tokyo | Tokyo Institute of Technology | The Information Theory that John von Neumann had in Mind
-- The Mechanism of Evolution by Thermodynamics, Logics and Digital Information -- Kimiaki Tokumaru (System Engineer) IT2011-33 |
Most people think of the name of Claude Shannon, when they hear about Information Theory. However, it was John von Neuma... [more] | IT2011-33 pp.55-60 |
| MSS, CAS, VLD, SIP | 2011-07-01 14:30 |
Okinawa | Okinawa-Ken-Seinen-Kaikan | Performance Evaluation of Various Configurations of Adder in Error Detection/Correction Circuits Kenta Ando, Atsushi Takahashi (Osaka Univ.) CAS2011-26 VLD2011-33 SIP2011-55 MSS2011-26 |
The performance of a circuit is improved by introducing error detection/correction mechanism which uses the variation of... [more] | CAS2011-26 VLD2011-33 SIP2011-55 MSS2011-26 pp.147-152 |
| DC | 2011-02-14 14:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Test Generation Method for Datapath Circuits Using Functional Time Expansion Models Teppei Hayakawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.) DC2010-65 |
Some large-scale integrated circuits have been recently designed at high-level by behavioral descriptions. Behavioral sy... [more] | DC2010-65 pp.39-44 |
| NLP, CAS | 2010-08-02 17:10 |
Tokushima | Naruto University of Education | [Invited Talk]
Some Problems on Nonlinear LC Circuits Hiroshi Kawakami CAS2010-46 NLP2010-62 |
A simple LC circuit is defined as a fundamental oscillatory circuit, if it has no L(or C) only cut-set and L(or C) only ... [more] | CAS2010-46 NLP2010-62 pp.69-72 |
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