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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
HWS, ICD |
2022-10-25 15:40 |
Shiga |
(Primary: On-site, Secondary: Online) |
Hardware Acceleration of TFHE-based Adder by Controlling Error Yinfan Zhao, Ikeda Makoto (Univ. of Tokyo) HWS2022-40 ICD2022-32 |
Fully homomorphic encryption (FHE) is expected to be used in the secure delegating computation. The bootstrapping in the... [more] |
HWS2022-40 ICD2022-32 pp.58-63 |
SCE |
2012-07-19 10:45 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Design of Circuits Controlling Dependence of Signal Propagation Time on Bias Voltage for Expanding the Operating Margin of SFQ Circuits Mikio Otsubo, Yuki Yamanashi, Nobuyuki Yoshikawa (YNU) SCE2012-10 |
Superconductive single flux quantum (SFQ) digital circuits can operate at a clock frequency of several tens GHz. However... [more] |
SCE2012-10 pp.7-11 |
ICD |
2009-12-14 13:30 |
Shizuoka |
Shizuoka University (Hamamatsu) |
[Poster Presentation]
Reducing pattern area technology of 3D transistor for system LSI Yu Hiroshima, Shigeyoshi Watanabe (Shonan Inst. of Tech.) ICD2009-78 |
We designed 1 bit Full Adder with FinFET, Double-Gate transistor. FinFET, Double-Gate transistor, Stacked type transisto... [more] |
ICD2009-78 pp.13-18 |
SDM, ED |
2009-06-25 09:00 |
Overseas |
Haeundae Grand Hotel, Busan, Korea |
[Invited Talk]
Novel-Functional Single-Electron Devices Using Silicon Nanodot Array Yasuo Takahashi, Takuya Kaizawa, Mingyu Jo, Masashi Arita (Hokkaido Univ.), Akira Fujiwar, Yukinori Ono (NTT), Hiroshi Inokawa (Shizuoka Univ.), Jung-Bum Choi (Chungbuk National Univ.) ED2009-83 SDM2009-78 |
We demonstrate a highly functional Si nanodot array device that operates by means of single-electron effects. The device... [more] |
ED2009-83 SDM2009-78 pp.145-148 |
VLD |
2009-03-13 15:15 |
Okinawa |
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Reduced pattern area technology of 3D transistor for system LSI Yu Hiroshima, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2008-167 |
We designed 1 bit Full Adder with FinFET, Double-Gate transistor. FinFET, Double-Gate transistor, Stacked type transisto... [more] |
VLD2008-167 pp.243-248 |
CAS, SIP, VLD |
2005-06-28 14:50 |
Miyagi |
Tohoku University |
Complementary Ferroelectric Capacitor Logic and its Application to Fully Parallel Arithmetic VLSI Shoun Matsunaga, Takahiro Hanyu (Tohoku Univ.) |
In this paper, we propose a Complementary Ferroelectric Capacitor Logic-in-Memory circuit that makes it possible easily ... [more] |
CAS2005-25 VLD2005-36 SIP2005-49 pp.61-65 |
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