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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2022-11-30 14:45 |
Kumamoto | (Primary: On-site, Secondary: Online) |
Evaluation of testing TSVs using the delay testable circuit implemented in a 3D IC Keigo Takami (Tokushima Univ. Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.)  VLD2022-47 ICD2022-64 DC2022-63 RECONF2022-70 |
Testing TSVs used for chip-to-chip interconnection in 3D stacked ICs is a challenging problem. We have proposed a bounda... [more] | VLD2022-47 ICD2022-64 DC2022-63 RECONF2022-70 pp.162-167 |
| DC | 2022-03-01 14:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. (Primary: On-site, Secondary: Online) |
Evaluation of Efficiency for a Method to Locate High Power Consumption with Switching Provability Ryu Hoshino, Taiki Utsunomiya, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2021-73 |
In recent years, as the high speed and miniaturization of LSIs have improved, it has become more difficult to test LSIs．... [more] | DC2021-73 pp.51-56 |
| DC | 2022-03-01 14:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. (Primary: On-site, Secondary: Online) |
SAT-based LFSR Seed Generation for Delay Fault BIST Kotaro Iwamoto, Satoshi Ohtake (Oita Univ.) DC2021-74 |
So far, a one-pass LFSR seed generation method for delay fault BIST has been proposed. The method directly generates see... [more] | DC2021-74 pp.57-62 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2020-11-17 10:30 |
Online | Online | Power Analysis Based on Probability Calculation of Small Regions in LSI Ryo Oba, Ryu Hoshino, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech) VLD2020-13 ICD2020-33 DC2020-33 RECONF2020-32 |
Power consumption in LSI testing is higher than in functional mode since more switching activities occur. High power con... [more] | VLD2020-13 ICD2020-33 DC2020-33 RECONF2020-32 pp.12-17 |
| DC | 2020-02-26 15:00 |
Tokyo | Improving Controllability of Signal Transitions in the High Switching Area of LSI Jie Shi, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2019-94 |
Power consumption in LSI testing is larger than in functional mode. High power consumption causes excessive IR-drop and ... [more] | DC2019-94 pp.49-54 |
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| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 13:50 |
Hiroshima | Satellite Campus Hiroshima | Study on the Applicability of ATPG Pattern for DFT Circuit Kohki Taniguchi, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2018-58 DC2018-44 |
With high integration of IC, small delay faults have occurred as the cause of a circuit failure. As a design-for-testabi... [more] | VLD2018-58 DC2018-44 pp.131-136 |
| DC | 2018-02-20 11:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Locating Hot Spots with Justification Techniques in a Layout Design Yudai Kawano, Kohei Miyase, Seiji Kajihara, Xiaoqing Wen (Kyutech) DC2017-80 |
In general, power consumption during LSI testing is higher than functional operation. Excessive power consumption in at-... [more] | DC2017-80 pp.19-24 |
| DC | 2017-12-15 15:30 |
Akita | Akita Study Center, The Open University of Japan | A Test Clock Observation Method Using Time-to-Digital Converters for Built-In Self-Test in FPGAs Yousuke Miyake, Yasuo Sato, Seiji Kajihara (KIT) DC2017-75 |
A delay measurement method combining a logic BIST with a variable test clock has been proposed to improve field reliabil... [more] | DC2017-75 pp.37-42 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-30 09:25 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Design of TDC Embedded in Scan FFs for Testing Small Delay Faults Shingo Kawatsuka, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2016-62 DC2016-56 |
With improvement of semiconductor manufacturing process, small delay becomes more important cause of timing failures. ... [more] |
VLD2016-62 DC2016-56 pp.105-110 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 10:50 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | On Correction of Temperature Influence to Delay Measurement in FPGAs Takeru Kina, Yousuke Miyake, Yasuo Sato, Seiji Kajihara (KIT) VLD2015-63 DC2015-59 |
As a means for delay testing for VLSIs in field, a measurement method of a path delay for a logic circuit using variable... [more] | VLD2015-63 DC2015-59 pp.165-170 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 14:10 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | An approach to LFSR/MISR seed generation for delay fault BIST Daichi Shimazu, Satishi Ohtake (Oita Univ.) VLD2015-70 DC2015-66 |
In this paper, we propose a method of LFSR/MISR seed generation for delay fault BIST. A widely used conventional way to... [more] |
VLD2015-70 DC2015-66 pp.213-218 |
| DC | 2015-06-16 15:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Method to Identify High Test Power Areas in Layout Design Kohei Miyase (Kyutech), Matthias Sauer, Bernd Becker (Univ. Freiburg), Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2015-18 |
The problems related to power consumption during at-speed testing is becoming more serious. Particularly, excessive peak... [more] | DC2015-18 pp.13-18 |
| DC | 2014-02-10 09:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A DFT Method to Achieve 100% Fault Coverage for QDI Asynchronous Circuit Sanae Mizutani, Hiroshi Iwata, Ken'ichi Yamaguchi (NNCT) DC2013-81 |
With the advances of semiconductor process technologies, synchronous circuits have serious problems of thr clock. Asynch... [more] | DC2013-81 pp.13-18 |
| DC | 2013-12-13 13:00 |
Ishikawa | Efficient Scan-Based BIST Architecture for Application-Dependent FPGA Test Keita Ito, Tomokazu Yoneda, Yuta Yamato, Kazumi Hatayama, Michiko Inoue (NAIST) DC2013-68 |
This paper presents a scan-based BIST architecture for testing of application-dependent circuits configured on FPGA. I... [more] |
DC2013-68 pp.1-6 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-29 09:45 |
Kagoshima | A Method of High Quality Transition Test Generation Using RTL Information Hiroyuki Nakashima, Satoshi Ohtake (Oita Univ.) VLD2013-94 DC2013-60 |
With the miniaturization and high speed of large scale integrated circuits (VLSIs), it has become important to test dela... [more] | VLD2013-94 DC2013-60 pp.239-244 |
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| IA | 2013-02-15 14:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Toward flexible network tester with FPGA Yohei Kuga, Takeshi Matsuya (Keio Univ.), Hiroaki Hazeyama (NAIST), Osamu Nakamura (Keio Univ.) IA2012-85 |
To measure performances of network hardware, there are methods of using the software and specialized hardware. Software... [more] |
IA2012-85 pp.89-94 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-29 09:25 |
Miyazaki | NewWelCity Miyazaki | Improvement of Test Data Compression Rate for Chiba-Scan Testing by Reconstructing Scan Chain Masato Akagawa, Kazuteru Namba, Hideo Ito (Chiba univ.) VLD2011-72 DC2011-48 |
Scan design is one of design for testing. Chiba-Scan proposed in 2005 is one of scan design for delay fault testing. Chi... [more] | VLD2011-72 DC2011-48 pp.121-126 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 10:30 |
Miyazaki | NewWelCity Miyazaki | On the design for testability method using Time to Digital Converter for detecting delay faults Hiroyuki Makimoto, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima) VLD2011-84 DC2011-60 |
We propose the design for testability method for detecting delay fault that can form a TDC(Time-to-Digital Converter) to... [more] | VLD2011-84 DC2011-60 pp.185-190 |
| DC | 2011-02-14 11:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An Analysis of Critical Paths for Field Testing with Process Variation Consideration Satoshi Kashiwazaki, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushuu Univ) DC2010-61 |
Recently, it has the problem that good VLSIs in production testing become defective VLSIs in the fields because small de... [more] | DC2010-61 pp.13-19 |
| DC | 2011-02-14 11:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Variation Aware Test Methodology Based on Statistical Static Timing Analysis Michihiro Shintani, Kazumi Hatayama, Takashi Aikyo (STARC) DC2010-62 |
The continuing miniaturization of LSI dimension may cause parametric faults which exceed the specification due to proces... [more] | DC2010-62 pp.21-26 |
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