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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SCE | 2019-01-23 13:30 |
Tokyo | Development of 30-GHz Datapath for Bit-Parallel, Gate-Level-Pipelined Rapid Single-Flux-Quantum Microprocessors Ikki Nagaoka (Nagoya Univ), Yuki Hatanaka (Mitsubishi Elec), Yuichi Matsui (Nagoya Univ), Koki Ishida (Kyushu Univ), Masamitsu Tanaka, Kyosuke Sano, Taro Yamashita (Nagoya Univ), Takatsugu Ono, Koji Inoue (Kyushu Univ), Akira Fujimaki (Nagoya Univ)  SCE2018-30 |
We have started development of high-throughput single-flux-quantum (SFQ) microprocessors with the aim of higher throughp... [more] | SCE2018-30 pp.29-34 |
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| SCE | 2017-10-05 11:15 |
Miyagi | Proposal of Parallel to Serial Conversion Circuit for 2-Dimension Superconductive Detector Array using Adiabatic Quantum-Flux-Parametron Fumihiro China, Naoki Takeuchi, Yuki Yamanashi, Nobuyuki Yoshikawa (YNU) SCE2017-29 |
Recently, the superconducting qubits and detectors have been studied well in fields such as quantum computing, quantum o... [more] | SCE2017-29 pp.41-46 |
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| SCE | 2017-08-09 14:35 |
Aichi | Nagoya Univ. (Higashiyama Campus) | Design of Component Circuits for Rapid Single-Flux-Quantum Gate-Level-Pipelined Microprocessors Yuki Hatanaka, Yuichi Matsui, Masamitsu Tanaka, Kyosuke Sano, Akira Fujimaki (Nagoya Univ.), Koki Ishida, Takatsugu Ono, Koji Inoue (Kyushu Univ.) SCE2017-17 |
We have started development of high-throughput rapid single-flux-quantum (RSFQ) microprocessors with the aim of higher p... [more] | SCE2017-17 pp.37-42 |
| RECONF, CPSY, DC, IPSJ-ARC (Joint) [detail] |
2017-05-22 17:10 |
Hokkaido | Noboribetsu-Onsen Dai-ichi-Takimoto-Kan | A proposal of Bit Serial Arithmetic Units for Arbitrary Precision Tomonori Miura, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2017-8 |
In this paper,we propose a bit serial arithmetic unit for arbitrary precision.It calculates 1 digit ev- ery cycle from t... [more] | RECONF2017-8 pp.37-41 |
| VLD, CAS, MSS, SIP | 2016-06-16 11:40 |
Aomori | Hirosaki Shiritsu Kanko-kan | A method of reducing amount of operations on the bit serial multiply-accumulator and its application Daichi Okamoto (Okayama Prefectural Univ.), Masafumi Kondo (Kawasaki Univ. of Medical Welfare), Yoshihiro Sejima, Tomoyuki Yokogawa, Kazutami Arimoto, Yoichiro Sato (Okayama Prefectural Univ.) CAS2016-7 VLD2016-13 SIP2016-41 MSS2016-7 |
Although the digital hearing aids with the high functionality of digital signal processor (DSP) becomes widely used, its... [more] | CAS2016-7 VLD2016-13 SIP2016-41 MSS2016-7 pp.35-40 |
| SCE | 2016-01-21 09:55 |
Tokyo | Improvement of operational stability of SFQ logic gate with optimized Josephson comparator Kenta Asakura, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama Nat Univ.) SCE2015-37 |
A single-flux-quantum (SFQ) circuits has been studied because of its low power and high-speed operation. Because the bit... [more] | SCE2015-37 pp.7-10 |
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| MSS, CAS, IPSJ-AL [detail] | 2015-11-21 11:15 |
Kagoshima | Ibusuki CityHall | A bit serial multiply and accumulator with negative number operation Daichi Okamoto (Okayama Prefectural Univ.), Masafumi Kondo (Kawasaki Univ. of Medical Welfare), Yoshihiro Sejima, Yoichiro Sato, Tomoyuki Yokogawa, Kazutami Arimoto (Okayama Prefectural Univ.) CAS2015-58 MSS2015-32 |
Recently, digital hearing aids with the high functionality of digital signal processor (DSP) become widely used, and thu... [more] | CAS2015-58 MSS2015-32 pp.115-120 |
| SCE | 2013-07-22 10:40 |
Tokyo | Kikaishinkou-kaikan Bldg. | Design and evaluation of the 2-bit Bit-Slice Adder based on 10kA/cm^2 process Kensuke Takata, Yuhi Hayakawa, Masamitsu Tanaka, Akira Fujimaki (Nagoya Univ.) SCE2013-12 |
A large number of researches on designing digital circuits by using SFQ logic circuits have been undertaken extensively.... [more] | SCE2013-12 pp.11-16 |
| SCE | 2012-07-19 11:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | SFQ Bit-Slice Floating Point Adder Yukio Ohmomo, Yohei Naruse (Kyoto Univ.), Nobutaka Kito (Chukyo Univ.), Naofumi Takagi, Kazuyoshi Takagi (Kyoto Univ.) SCE2012-11 |
Single Flux Quantum (SFQ) circuits operate at high-speed with low-power consumption. A Large-Scale Reconfigurable Data ... [more] |
SCE2012-11 pp.13-17 |
| RECONF | 2009-09-18 09:00 |
Tochigi | Utsunomiya Univ. | A Proposal for a Method to Generate Optimized Dataflow for Reconfigurable Processor DS-HIE Based on Bit Serial Operation Yasuhiro Nishinaga, Ken'ichi Umeda, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.) RECONF2009-28 |
Our laboratory has developed a reconfigurable processor DS-HIE based on bit-serial operation. The DS-HIE processor achie... [more] | RECONF2009-28 pp.55-60 |
| RECONF | 2009-09-18 09:25 |
Tochigi | Utsunomiya Univ. | Consideration of Data Transfer Unit in Reconfigurable Processor DS-HIE Ken'ichi Umeda, Yasuhiro Nishinaga, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ) RECONF2009-29 |
We have developed reconfigurable processor DS-HIE based on bit-serial operation. The merit of bit-serial operation is th... [more] | RECONF2009-29 pp.61-66 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 16:25 |
Fukuoka | Kitakyushu International Conference Center | Initial Evaluation of FIR Filter Based on Digit-Serial Computation Yuhki Yamabe, Kazuya Tanigawa, Tetsuo Hironaka (HCU) VLD2007-81 DC2007-36 |
Increasing the filter-length and bit-width of the FIR filter designed using the conventional parallel operation units, w... [more] | VLD2007-81 DC2007-36 pp.67-72 |
| VLD, IPSJ-SLDM | 2007-05-11 11:20 |
Kyoto | Kyodai Kaikan | An SIMD MSD Multiplier based on variable GF($2^m$) for Elliptic Curve Cryptosystem Ryuta Nara, Kazunori Shimizu, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2007-11 |
Originally elliptic curve cryptosystem (ECC) hardware are often required to operate variable key length. Digit-serial mu... [more] | VLD2007-11 pp.25-29 |
| SCE | 2007-01-26 10:55 |
Tokyo | SRL | Design and Implementation of Bit-Slice Adder Heejoung Park, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama National Univ.), Masamitsu Tanaka, Akira Fujimaki (Nagoya Univ.), Hirotaka Terai (NICT), Shinichi Yorozu (NEC) |
Recently, a lot of researches on designing digital circuits by using SFQ logic circuits have been carried out extensivel... [more] | SCE2006-32 pp.13-18 |
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