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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SCE | 2012-07-19 10:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Design of Circuits Controlling Dependence of Signal Propagation Time on Bias Voltage for Expanding the Operating Margin of SFQ Circuits Mikio Otsubo, Yuki Yamanashi, Nobuyuki Yoshikawa (YNU)  SCE2012-10 |
Superconductive single flux quantum (SFQ) digital circuits can operate at a clock frequency of several tens GHz. However... [more] | SCE2012-10 pp.7-11 |
| SCE | 2012-07-19 11:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | SFQ Bit-Slice Floating Point Adder Yukio Ohmomo, Yohei Naruse (Kyoto Univ.), Nobutaka Kito (Chukyo Univ.), Naofumi Takagi, Kazuyoshi Takagi (Kyoto Univ.) SCE2012-11 |
Single Flux Quantum (SFQ) circuits operate at high-speed with low-power consumption. A Large-Scale Reconfigurable Data ... [more] |
SCE2012-11 pp.13-17 |
| AI | 2011-05-26 10:30 |
Tokyo | Kwansei Gakuin Univ. Tokyo Marunouchi Campus | Several Remarks on the Acquisition of Web-Information
-- Co-existence of Bit and Linguistic Information, and Corporal Intelligence -- Kimiaki Tokumaru (System Engineer) AI2011-1 |
The author has been investigating on the origin and mechanism of language through interdisciplinary researches. He reali... [more] | AI2011-1 pp.1-6 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] | 2011-03-18 11:20 |
Okinawa | Design Method of Easily Testable Parallel Adders under Delay Constraints Shinichi Fujii (Nagoya Univ.), Naofumi Takagi (Kyoto Univ.) CPSY2010-75 DC2010-74 |
Recently, with the development of VLSI design and manufacturing technology, the scale of integrated circuits on a VLSI c... [more] | CPSY2010-75 DC2010-74 pp.57-62 |
|
| ICD | 2010-12-16 15:10 |
Tokyo | RCAST, Univ. of Tokyo | [Poster Presentation]
Study on CMOS R-2R Ladder for Linearity Optimization by Adjust Channel Width Yuta Kato, Cong-Kha Pham (UEC) ICD2010-105 |
In this paper, we present the method of how to optimize the linear CMOS R-2R ladder by adjusting the channel width. We c... [more] | ICD2010-105 pp.59-63 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-12-01 14:50 |
Fukuoka | Kyushu University | Optimal adder architecture in ultra low voltage domain Nao Konishi, Masaru Kudo, Kimiyoshi Usami (Shibaura Inst. Tech.) VLD2010-81 DC2010-48 |
Circuit performance is evaluated for several adder architectures with wiring capacitance extracted from layout at 65nm p... [more] | VLD2010-81 DC2010-48 pp.173-178 |
| SCE | 2010-10-19 16:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | High-Speed Test of Circuit Components of SFQ Radix-2 Butterfly Processor using 10 kA/cm<sup>2</sup> Nb Advanced Process Fumishige Miyaoka, Yasuhiro Shimamura, Toshiki Kainuma, Yuki Yamanashi, Nobuyuki Yoshikawa (YNU) SCE2010-34 |
A large amount of data processing at extremely high speed is necessary in real-time FFT (Fast Fourier Transform). Howeve... [more] | SCE2010-34 pp.61-66 |
| US | 2010-09-29 16:40 |
Miyagi | Tohoku Univ. | Consideration on ladder-type SAW filters with wide frequency tuning range Nobuyuki Nakamura, Tomoya Komatsu, Tatsuya Omori, Ken-ya Hashimoto, Masatsune Yamaguchi (Chiba Univ.) US2010-56 |
This paper discusses tunable SAW filters using the ladder-type configuration with wide frequency tuning range. First, we... [more] | US2010-56 pp.45-48 |
| MW | 2010-09-09 13:30 |
Tokyo | Tokyo Inst. of Tech. | Q-Factors of Oscillator Feedback Circuits Composed of Transmission Line Yoshitada Iyama (Kumamoto National College of Technology) MW2010-66 |
Q-factor formulas for low pass type phase shift ladder networks have been derived. They are described as a function of t... [more] | MW2010-66 pp.1-6 |
| ICD (Workshop) |
2010-08-16 - 2010-08-18 |
Overseas | Ho Chi Minh City University of Technology | High Performance Hybrid Wave-Pipelined Adder Using A Gain Based Delay Model Truong Thi Kim Tuoi, Jubee Tada, Gensuke Goto (Yamagata Univ.) |
This paper describes a hybrid wave-pipelined adder using a gain based delay model in order to balance the delays in a co... [more] | |
| CQ | 2010-07-08 13:45 |
Hokkaido | Soya Fureai Park | Analysis of effects on wideband speech for elderly people by laddering method Atsuko Kurashima, Toshiko Tominaga, Takanori Hayashi, Akira Takahashi (NTT) CQ2010-25 |
Communication services considering elderly people are needed because of aging society. We studied a subjective quality e... [more] | CQ2010-25 pp.51-54 |
| MW | 2010-05-14 09:55 |
Hyogo | University of Hyogo | Design Method of Lumped-Element Dual-Bnad Wilkinson Power Dividers Hiroyuki Mizuno, Tadashi Kawai, Isao Ohta, Akira Enokihara (Univ. of Hyogo) MW2010-21 |
This paper treats a design method of dual-band lumped-element Wilkinson power dividers using series and parallel LC-reso... [more] | MW2010-21 pp.39-43 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-UBI, IPSJ-MBL [detail] | 2010-03-28 14:35 |
Tokyo | A consideration of synthesis methods for easily testable parallel prefix adders Shinichi Fujii, Naofumi Takagi (Nagoya Univ.) CPSY2009-93 DC2009-90 |
Previously, synthesis methods of parallel prefix adders have been proposed. These methods primarily use circuit area and... [more] | CPSY2009-93 DC2009-90 pp.489-493 |
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| VLD | 2010-03-11 15:25 |
Okinawa | Analytical Evaluation of Average Switching Energy of Adders Shinji Ohno, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ.) VLD2009-116 |
As fundamental evaluation bases of VLSI circuits, there are the area, computation time (delay), and energy consumption. ... [more] | VLD2009-116 pp.103-107 |
|
| ICD | 2009-12-14 13:30 |
Shizuoka | Shizuoka University (Hamamatsu) | [Poster Presentation]
Reducing pattern area technology of 3D transistor for system LSI Yu Hiroshima, Shigeyoshi Watanabe (Shonan Inst. of Tech.) ICD2009-78 |
We designed 1 bit Full Adder with FinFET, Double-Gate transistor. FinFET, Double-Gate transistor, Stacked type transisto... [more] | ICD2009-78 pp.13-18 |
| SCE | 2009-10-20 13:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Design of SFQ Floating-Point Units Using Nb Advanced Process Toshiki Kainuma, Yasuhiro Shimamura, Fumishige Miyaoka, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama Nat. Univ.), Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi (Nagoya Univ.) SCE2009-19 |
We are developing a large-scale reconfigurable data-path (LSRDP) based on the single-flux-quantum (SFQ) circuits, which ... [more] | SCE2009-19 pp.13-18 |
| MW | 2009-06-30 15:25 |
Aichi | Nagoya Institute of Technology | Compensation Method of Intermodulation Distortion by Thermal Memory Effect for Microwave Power Amplifiers Junichi Kimura, Ryo Ishikawa, Yukio Takahashi, Kazuhiko Honjo (The Univ. of Electro-Comm.) MW2009-27 |
A compensation method for 3rd order Intermodulation Distortion (IMD3) caused by a thermal memory effect in microwave pow... [more] | MW2009-27 pp.45-50 |
| SDM, ED | 2009-06-25 09:00 |
Overseas | Haeundae Grand Hotel, Busan, Korea | [Invited Talk]
Novel-Functional Single-Electron Devices Using Silicon Nanodot Array Yasuo Takahashi, Takuya Kaizawa, Mingyu Jo, Masashi Arita (Hokkaido Univ.), Akira Fujiwar, Yukinori Ono (NTT), Hiroshi Inokawa (Shizuoka Univ.), Jung-Bum Choi (Chungbuk National Univ.) ED2009-83 SDM2009-78 |
We demonstrate a highly functional Si nanodot array device that operates by means of single-electron effects. The device... [more] | ED2009-83 SDM2009-78 pp.145-148 |
| DC | 2009-06-19 10:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Design method of easily testable parallel prefix adders Hidetoshi Suzuki, Naofumi Takagi (Nagoya Univ) DC2009-10 |
We propose a design method of easily testable parallel prefix adders. In a parallel prefix adder, the prefix computation... [more] | DC2009-10 pp.1-6 |
| VLD | 2009-03-13 15:15 |
Okinawa | Reduced pattern area technology of 3D transistor for system LSI Yu Hiroshima, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2008-167 |
We designed 1 bit Full Adder with FinFET, Double-Gate transistor. FinFET, Double-Gate transistor, Stacked type transisto... [more] | VLD2008-167 pp.243-248 |
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