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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD | 2015-03-04 13:00 |
Okinawa | Okinawa Seinen Kaikan | An Evaluation of the Performance of a Multiplier in Error-detection/correction-framework Satoshi Ohtsuki, Atsushi Takahashi (Tokyo Tech)  VLD2014-181 |
In the current typical of integrated circuits, the performance is determined by the maximum delay between flip-flops. Th... [more] | VLD2014-181 pp.159-164 |
| EMCJ, IEE-EMC | 2014-12-19 16:05 |
Shizuoka | Shizuoka Univ. | Security Evaluation of CSSAL Countermeasure against Side-Channel Attacks Using Frequency Spectrum Analysis Cancio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine (Gifu Univ.) EMCJ2014-82 |
Information leakage on cryptographic devices are possible because of the correlation between the processed data and its ... [more] | EMCJ2014-82 pp.75-80 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 16:40 |
Oita | B-ConPlaza | A complex multiplier using two floating-point fused multiply-add unit Yuhei Takata, Naofumi Takagi, Kazuyoshi Takagi (Kyoto Univ.) CPSY2014-76 |
Complex operations are used in scientific computing and signal processing. Floating-point complex multiplication is imp... [more] |
CPSY2014-76 pp.25-29 |
| CAS, MSS, IPSJ-AL [detail] | 2014-11-20 10:40 |
Okinawa | Nobumoto Ohama Memorial Hall (Ishigaki island) | An asynchronous serial multiplier for digital fearing aid Masafumi Kondo, Daichi Okamoto (Kawasaki Univ. of Medical Welfare), Yoichiro Sato, Tomoyuki Yokogawa, Kazutami Arimoto (Okayama Prefectural Univ.) CAS2014-89 MSS2014-53 |
Recently, digital hearing aids with digital signal processor (DSP) become widely used because of increasing of hearing i... [more] | CAS2014-89 MSS2014-53 pp.11-16 |
| DC | 2014-06-20 15:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Floating-point Multiplier with Reduced Precision Error Checking by Partial Duplication Nobutaka Kito (Chukyo Univ.), Kazushi Akimoto, Naofumi Takagi (Kyoto Univ.) DC2014-15 |
We propose a floating-point multiplier with reduced precision error checking. The multiplier uses a truncated multiplie... [more] |
DC2014-15 pp.33-38 |
| VLD, IPSJ-SLDM | 2014-05-29 13:50 |
Fukuoka | Kitakyushu International Conference Center | SOTB 65nm CMOS Design of Gate-Level Dual Pipeline Self-Synchronous Wallace Tree Multiplier Masato Tamura, Makoto Ikeda (Univ. of Tokyo) VLD2014-8 |
Thanks to recent advances, the size of transistor shrinks and degree of integration becomes high. Butbecause of that adv... [more] | VLD2014-8 pp.39-44 |
| SCE | 2014-01-24 13:40 |
Tokyo | Kikaishinkou-kaikan Bldg. | Comparison of the final addition circuit in SFQ parallel multiplier with a tree structure partial product adder circuit Akifumi Yamada, Takeshi Onomi, Koji Nakajima (Tohoku Univ.) SCE2013-52 |
A single flux quantum (SFQ) circuit is capable of high-speed operation in a few 10 GHz, and it has a big advantage compa... [more] | SCE2013-52 pp.101-104 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] | 2013-03-14 15:30 |
Nagasaki | Multiplier with concurrent error detection by particial duplication Kazushi Akimoto (Kyoto Univ.), Nobutaka Kito (Cyukyo Univ.), Naofumi Takagi (Kyoto Univ.) CPSY2012-99 DC2012-105 |
We propose a multiplier with concurrent error detection, which can detect the error more than the designated numerical v... [more] | CPSY2012-99 DC2012-105 pp.283-287 |
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| SCE | 2012-07-19 11:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Design of a 2bit Bit-Slice Half-Precision Floating-Point Multiplier Using SFQ Circuits Yohei Naruse (Kyoto Univ.), Nobutaka Kito (Chukyo Univ.), Naofumi Takagi (Kyoto Univ.) SCE2012-12 |
Single flux quantum (SFQ) circuits are expected as next-generation circuits. Arithmetic circuits using SFQ circuits ha... [more] |
SCE2012-12 pp.19-23 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 09:00 |
Miyazaki | NewWelCity Miyazaki | A Circuit Partitioning Strategy for 3-D Integrated Floating-point Multipliers Kazushige Kawai, Jubee Tada (Yamagata Univ.), Ryusuke Egawa, Hiroaki Kobayashi (Tohoku Univ.), Gensuke Goto (Yamagata Univ.) CPM2011-162 ICD2011-94 |
Three-dimensional (3-D) integration technologies are attractive for enhancing the speed of the arithmetic circuits. To i... [more] | CPM2011-162 ICD2011-94 pp.67-72 |
| SCE | 2011-07-13 15:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | High-Throuput Bit-Slice Multipliers Using SFQ Circuits Yohei Naruse, Nobutaka Kito, Naofumi Takagi (Kyoto Univ.) SCE2011-9 |
Single flux quantum (SFQ) circuits are expected as next-generation circuits. Arithmetic circuits using SFQ circuits have... [more] | SCE2011-9 pp.47-52 |
| ICD | 2010-12-17 15:15 |
Tokyo | RCAST, Univ. of Tokyo | A Circuit Partitioning Strategy for 3-D Integrated Multipliers Kazuhito Sakai, Jubee Tada (Yamagata Univ.), Ryusuke Egawa, Hiroaki Kobayashi (Tohoku Univ.), Gensuke Goto (Yamagata Univ.) ICD2010-125 |
Three-dimensional(3-D) integration technologies attract a lot of attention to further enhance the performance of the LSI... [more] | ICD2010-125 pp.153-158 |
| ICD | 2010-12-17 15:40 |
Tokyo | RCAST, Univ. of Tokyo | Design of a Low Error LUT-based Truncated Multiplier Van-Phuc Hoang, Cong-Kha Pham (Univ. of Electro-comm.) ICD2010-126 |
Truncated multiplication is an efficient method to reduce area and power consumption of multipliers in signal processing... [more] | ICD2010-126 pp.159-162 |
| SCE | 2010-10-19 16:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | High-Speed Test of Circuit Components of SFQ Radix-2 Butterfly Processor using 10 kA/cm<sup>2</sup> Nb Advanced Process Fumishige Miyaoka, Yasuhiro Shimamura, Toshiki Kainuma, Yuki Yamanashi, Nobuyuki Yoshikawa (YNU) SCE2010-34 |
A large amount of data processing at extremely high speed is necessary in real-time FFT (Fast Fourier Transform). Howeve... [more] | SCE2010-34 pp.61-66 |
| SCE | 2010-07-22 14:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | 50 GHz Tests of SFQ Floating-Point Multipliers Using 10 kA/cm2 Nb Advanced Process Yasuhiro Shimamura, Toshiki Kainuma, Fumishige Miyaoka, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama National Univ.), Akira Fujimaki, Kazuyoshi Takagi (Nagoya Univ.), Naofumi Takagi (Kyoto Univ.) SCE2010-22 |
We have been developing a large-scale reconfigurable data-path (LSRDP) using single-flux-quantum (SFQ) circuit to realiz... [more] | SCE2010-22 pp.47-52 |
| SIP, CAS, CS | 2010-03-02 13:45 |
Okinawa | Hotel Breeze Bay Marina, Miyakojima | Improvement of Linearity of CMOS Analog Multiplier using Feed-Forward Error Correction Yasuaki Mabuchi, Yohtaro Umeda, Osamu Takyu (Tokyo Univ. of Science) CAS2009-138 SIP2009-183 CS2009-133 |
Analog multiplier is an important function block, and used in various systems. However, high input voltage causes improp... [more] | CAS2009-138 SIP2009-183 CS2009-133 pp.285-290 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-04 15:00 |
Kochi | Kochi City Culture-Plaza | Evaluation of Energy Consumption on Multipliers Using the Sum of Operands Hirotaka Kawashima, Naofumi Takagi (Nagoya Univ.) VLD2009-66 DC2009-53 |
We evaluate dynamic energy consumption of multipliers using the sum of operands we have proposed before. The multiplie... [more] |
VLD2009-66 DC2009-53 pp.173-178 |
| SCE | 2009-10-20 13:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Design of SFQ Floating-Point Units Using Nb Advanced Process Toshiki Kainuma, Yasuhiro Shimamura, Fumishige Miyaoka, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama Nat. Univ.), Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi (Nagoya Univ.) SCE2009-19 |
We are developing a large-scale reconfigurable data-path (LSRDP) based on the single-flux-quantum (SFQ) circuits, which ... [more] | SCE2009-19 pp.13-18 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 10:55 |
Fukuoka | Kitakyushu Science and Research Park | Evaluation of Hardware Algorithms on a Circuit Model Considering Wire Delay Tetsuya Nagase, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ.) VLD2008-77 DC2008-45 |
In the design of integrated circuits, it is important to design or choose algorithms according to the requirements such ... [more] | VLD2008-77 DC2008-45 pp.103-108 |
| DC | 2008-06-20 14:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg | Test generation for multi-operand adders consisting of full adders Nobutaka Kito, Naofumi Takagi (Nagoya Univ.) DC2008-14 |
Level-testability of multi-operand adders consisting of carry save adders is shown by showing test design for it. Carry ... [more] | DC2008-14 pp.19-22 |
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