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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
QIT (2nd) |
2022-12-08 14:00 |
Kanagawa |
Keio Univ. (Primary: On-site, Secondary: Online) |
[Poster Presentation]
Universal quantum computation using qubit array that is controllable only in units of column and row Saki Tanaka, Tatsuya Tomaru, Chihiro Yoshimura, Hiroyuki Mizuno (HITACHI) |
two-dimensional qubit array can be highly integrated by making the control lines common in units of column and row. Sing... [more] |
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SDM, ICD, ITE-IST [detail] |
2019-08-07 13:30 |
Hokkaido |
Hokkaido Univ., Graduate School /Faculty of Information Science and |
[Invited Talk]
A Scalable CMOS Annealing Processor for Solving Large-scale Combinatorial Optimization Problems Masato Hayashi, Takashi Takemoto, Chihiro Yoshimura, Masanao Yamaoka (Hitachi) SDM2019-36 ICD2019-1 |
This paper presents a CMOS annealing processor (CMOS-AP) that accelerates ground state searches of the Ising model. The ... [more] |
SDM2019-36 ICD2019-1 pp.1-5 |
COMP, IPSJ-AL |
2016-06-25 13:40 |
Ishikawa |
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Contractive graph-minor embedding for CMOS Ising computer Takuya Okuyama, Chihiro Yoshimura, Masato Hayashi, Saki Tanaka, Masanao Yamaoka (Hitachi) COMP2016-11 |
We proposed CMOS Ising computer, which maps the combinatorial optimization problems to the ground state search of Ising ... [more] |
COMP2016-11 pp.97-103 |
ICD |
2015-04-17 14:55 |
Nagano |
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[Invited Talk]
An 1800-Times-Higher Power-Efficient 20k-spin Ising Chip for Combinatorial Optimization Problem with CMOS Annealing Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno (Hitachi) ICD2015-13 |
A new computing architecture using Ising model that effectively solves combinatorial optimization problems is proposed, ... [more] |
ICD2015-13 pp.63-68 |
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