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Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Kimiyoshi Usami (Shibaura Inst. of Tech.)
Vice Chair Akihisa Yamada (Sharp)
Secretary Kazutoshi Kobayashi (Kyoto Inst. of Tech.), Takashi Takenaka (NEC)

Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [schedule] [select]
Chair Michiaki Muraoka (Kochi Univ.)
Secretary Hiroaki Komatsu (Fujitsu), Naoki Iwata (Sony), Nozomu Togawa (Waseda Univ.)

Conference Date Wed, May 30, 2012 14:30 - 17:20
Thu, May 31, 2012 09:30 - 11:45
Topics System Design, etc. 
Conference Place Kitakyushu International Conference Center 
Transportation Guide http://www.convention-a.jp/access/
Contact
Person
Prof. Shigetoshi Nakatake
+81-93-695-3268
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

Wed, May 30 PM  System Design
Chair: Hiroshi Saito (Univ. of Aizu)
14:30 - 16:10
(1)
VLD
14:30-14:55 Task Allocation Optimization Method Using SA Method to Automatically Set Starting Temperature for Multi-Processor System VLD2012-1 Yuichiro Yanabu, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.)
(2)
VLD
14:55-15:20 Multiple supply voltages aware high-speed and high-efficient high-level synthesis for HDR architectures VLD2012-2 Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
(3)
VLD
15:20-15:45 Write Control Method Based on State Transition for Magnetic Flip-Flop VLD2012-3 Naoya Okada (Waseda Univ.), Yuichi Nakamura (NEC), Shinji Kimura (Waseda Univ.)
(4)
VLD
15:45-16:10 High-level Design Debugging Using Potential Dependence VLD2012-4 Shohei Ono, Takeshi Matsumoto, Masahiro Fujita (Univ. of Tokyo)
  16:10-16:20 Break ( 10 min. )
Wed, May 30 PM  Invited Talk
Chair: Kimiyoshi Usami (Shibaura Inst. Tech.)
16:20 - 17:20
(5) 16:20-17:20 [Invited Talk]
How to Mitigate Reliability-related Issues on Nano-scaled LSIs VLD2012-5
Kazutoshi Kobayashi (KIT)
Thu, May 31 AM  Physical Design
Chair: Yukihide Kohira (Univ. of Aizu)
09:30 - 10:45
(6)
VLD
09:30-09:55 Sub-path delay estimation for reconvergent path VLD2012-6 Seiya Nagatsuka, Yasuhiro Takashima (Univ. of Kitakyushu)
(7)
VLD
09:55-10:20 A Placement Method on Overlapped Printed-Wiring-Boards VLD2012-7 Tetsuya Matsuura, Kunihiro Fujiyoshi (TUAT)
(8)
VLD
10:20-10:45 A Comparator Energy Model Considering Shallow Trench Isolation by Geometric Programming VLD2012-8 Gong Chen, Yu Zhang, Bo Yang, Qing Dong, Shigetoshi Nakatake (Kitakyushu Univ.)
  10:45-10:55 Break ( 10 min. )
Thu, May 31 AM  Design Environment
Chair: Yasuhiro Takashima (Univ. of Kitakyushu)
10:55 - 11:45
(9)
VLD
10:55-11:20 Development of an FPGA Design Support Tool Set for Asynchronous Circuits with Bundled-data Implementation VLD2012-9 Keitaro Takizawa, Minoru Iizuka, Hiroshi Saito (Univ. of Aizu)
(10)
VLD
11:20-11:45 Statistical Analysis and its Hardware Implementation on Simulation Results of Systems with Uncertain Inputs VLD2012-10 Kosuke Oshima, Shohei Ono, Takeshi Matsumoto, Masahiro Fujita (Univ. of Tokyo)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Kazutoshi Kobayashi (Kyoto Institute of Technology)
E-: bat
Tel: +81-75-724-7452 
Announcement See also VLD's homepage:
http://www.ieice.org/~vld/
IPSJ-SLDM Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)   [Latest Schedule]
Contact Address Nozomu Togawa (Waseda University)
E sldm2012g 
Announcement See also SLDM homepage:
http://www.sig-sldm.org/


Last modified: 2012-05-14 15:18:30


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