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Technical Committee on Reconfigurable Systems (RECONF) (Searched in: 2015)
Search Results: Keywords 'from:2015-06-19 to:2015-06-19'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF | 2015-06-19 10:00 |
Kyoto | Kyoto University | [Special Talk]
Semiconductor Innovation seen from Makimoto's Wave and its Impact Tsugio Makimoto (SSIS)  RECONF2015-1 |
Nearly a quarter century has passed since Makimoto’s Wave was introduced to the public in 1991. In the meantime, the sem... [more] | RECONF2015-1 pp.1-6 |
| RECONF | 2015-06-19 11:10 |
Kyoto | Kyoto University | Power optimization of low-power reconfigurable accelerator CMA-SOTB Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano (Keio Univ.) RECONF2015-2 |
[more] | RECONF2015-2 pp.7-12 |
| RECONF | 2015-06-19 11:35 |
Kyoto | Kyoto University | Evaluation of the third Flex Power FPGA chip in SOTB technology Masakazu Hioki, Yasuhiro Ogasahara, Hanpei Koike (AIST) RECONF2015-3 |
This paper reports the evaluation of the third Flex Power FPGA chip in SOTB technology. Fabricated chip aims to shrink a... [more] | RECONF2015-3 pp.13-16 |
| RECONF | 2015-06-19 12:00 |
Kyoto | Kyoto University | An Area Optimization of 3D FPGA with high speed inter-layer communication link Yuto Takeuchi, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ) RECONF2015-4 |
Three-dimensional (3D) stacking technology is attractive for providing another way to improve the performance of the lar... [more] | RECONF2015-4 pp.17-22 |
| RECONF | 2015-06-19 13:20 |
Kyoto | Kyoto University | A Classification Hardware with Hierarchical Multiple Scan Window Sizes for Colorectal Endoscopic Diagnosis Takumi Okamoto, Tetsushi Koide, Tatsuya Shimizu, Koki Sugi, Anh-Tuan Hoang, Hikaru Satoh, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda (Hiroshima Univ.), Shigeto Yoshida, Hiroshi Mieno (Hiroshima General Hospital of West Japan Railway Company), Shinji Tanaka (Hiroshima Univ.) RECONF2015-5 |
With the increase of colorectal cancer patients in recent years, the needs of quantitative evaluation of colorectal canc... [more] | RECONF2015-5 pp.23-28 |
| RECONF | 2015-06-19 13:45 |
Kyoto | Kyoto University | Consideration for Visual Word Feature Transformation Hardware based on Bag-of-Features Koki Sugi, Tetsushi Koide, Tatsuya Shimizu, Takumi Okamoto, Anh-Tuan Hoang, Hikaru Satoh, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda (Hiroshima Univ.), Shigeto Yoshida, Hiroshi Mieno (Hiroshima General Hospital of West Japan Railway Company), Shinji Tanaka (Hiroshima Univ.) RECONF2015-6 |
Recent years, the Computer-Aided Diagnosis (CAD) system which supports doctor’s diagnosis effectively in the diagnosis o... [more] | RECONF2015-6 pp.29-34 |
| RECONF | 2015-06-19 14:10 |
Kyoto | Kyoto University | High Speed Calculation of Convex Hull in 2D Images using FPGA Kahori Kemmotsu, Kenji Kanazawa, Yamato Mori (Univ. of Tsukuba), Noriyuki Aibe (SUSUBOX), Moritoshi Yasunaga (Univ. of Tsukuba) RECONF2015-7 |
Given a set of points, a convex hull is the smallest convex polygon containing all the points. In this paper, we describ... [more] | RECONF2015-7 pp.35-40 |
| RECONF | 2015-06-19 14:35 |
Kyoto | Kyoto University | ROS compliant componentizing of image processing hardware on a Programmable SoC Kazushi Yamashina, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota (Utsunomiya Univ.) RECONF2015-8 |
In recent years, robots are expected to be autonomous, and their control software become complex and highly functional. ... [more] | RECONF2015-8 pp.41-46 |
| RECONF | 2015-06-19 15:10 |
Kyoto | Kyoto University | Consideration of the one-dimensional array processor suitable for a shock tube problem by FPGA Keisuke Hirofuji, Ryo Okuda, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ) RECONF2015-9 |
[more] | RECONF2015-9 pp.47-52 |
| RECONF | 2015-06-19 15:35 |
Kyoto | Kyoto University | Realization of FPGA Control Processing with Functional Safety Kenichi Morimoto (Nagasaki Univ.), Masanori Nobe (MHPS), Masaharu Tanaka (MHI), Yuichiro Shibata, Yudai Shirakura, Hidenori Maruta, Fujio Kurokawa (Nagasaki Univ.) RECONF2015-10 |
This paper presents a design approach of FPGA for the main processing unit in the industrial control systems. It is clar... [more] | RECONF2015-10 pp.53-57 |
| RECONF | 2015-06-19 16:00 |
Kyoto | Kyoto University | An arithmetic design approach with diversity and redundancy for FPGAs Yudai Shirakura, Kenichi Morimoto (Nagasaki Univ.), Masanori Nobe (MHPS), Masaharu Tanaka (MHI), Yuichiro Shibata, Hidenori Maruta, Fujio Kurokawa (Nagasaki Univ.) RECONF2015-11 |
While application of FPGAs in control systems of industrial infrastructures is promising, a warranty of the functional s... [more] | RECONF2015-11 pp.59-63 |
| RECONF | 2015-06-19 16:25 |
Kyoto | Kyoto University | Towards the Fastest FPGA-based Sorting Hardware in the World Ryohei Kobayashi, Kenji Kise (Tokyo Tech) RECONF2015-12 |
Sorting is an extremely important computation kernel that has been accelerated by using FPGAs in a lot of fields, such a... [more] | RECONF2015-12 pp.65-70 |
| RECONF | 2015-06-19 17:00 |
Kyoto | Kyoto University | [Invited Talk]
Reliability on Integrated Circuits Kazutoshi Kobayashi (Kyoto Inst. of Tech.) RECONF2015-13 |
[more] | RECONF2015-13 p.71 |
| RECONF | 2015-06-20 09:30 |
Kyoto | Kyoto University | A SW/HW Interface Implementation Method in the System Design Environment for Programmable SoCs Yusuke Tani, Takuya Hatayama, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.) RECONF2015-14 |
A programmable SoC, which integrates processors and FPGA on the same chip, has become attracted attention in embedded sy... [more] | RECONF2015-14 pp.73-78 |
| RECONF | 2015-06-20 09:55 |
Kyoto | Kyoto University | A Near-memory Processing Architecture on FPGAs for Data Movement Intensive Applications Vu Hoang Gia, Tran Thi Hong, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) RECONF2015-15 |
Memory latency is the most serious design concern in computing centric architectures integrated with cache levels as a d... [more] | RECONF2015-15 pp.79-84 |
| RECONF | 2015-06-20 10:20 |
Kyoto | Kyoto University | Implementation and Applications of An Efficient Parallel Architecture for Matrix Calculations Yuki Murakami, Naohito Nakasato, S. Sedukhin (Univ. of Aizu) RECONF2015-16 |
Matrix calculations are a fundamental tool in scientific and engineering applications. In our previous work, we have pro... [more] | RECONF2015-16 pp.85-90 |
| RECONF | 2015-06-20 10:45 |
Kyoto | Kyoto University | A Deep Convolutional Neural Network Based on Nested Residue Number System Hiroki Nakahara (Ehime Univ.), Tsutomu Sasao (Meiji Univ.) RECONF2015-17 |
A pre-trained deep convolutional neural network~(DCNN) is the feedforward computation perspective which is widely used f... [more] | RECONF2015-17 pp.91-96 |
| RECONF | 2015-06-20 11:10 |
Kyoto | Kyoto University | A Rapid Verification Environment for Statistical Evaluation of PUF Circuits Toshihiro Katashita, Yasunori Onda, Yohei Hori (AIST) RECONF2015-18 |
In this study, we constructed a rapid experimentation environment for Physically Unclonable Function (PUF) circuit verif... [more] | RECONF2015-18 pp.97-102 |
| RECONF | 2015-06-20 11:35 |
Kyoto | Kyoto University | FPGA Implementation of a key generation circuit using PUF and Fuzzy Extractor on SASEBO-G3 Yohei Hori, Toshihiro Katashita (AIST) RECONF2015-19 |
We implemented a key generation circuit using a Physically Unclonable Function (PUF) and Fuzzy Extractor (FE) to a Kinte... [more] | RECONF2015-19 pp.103-108 |
| RECONF | 2015-06-20 13:10 |
Kyoto | Kyoto University | Introduction to 2015 FPGA Trax contest Yasunori Osana (Univ. of the Ryukyus), Tomonori Izumi (Ritsmeikan Univ.), Takefumi Miyoshi (e-trees), Hiroki Nakahara (Ehime Univ.) RECONF2015-20 |
In 2015 IEICE RECONF design contest, Trax, a new board game is introduced. This paper briefly describes its rule, commun... [more] | RECONF2015-20 pp.109-112 |
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