Thu, May 10 PM Architecture
Chair: Kiyoharu Hamaguchi (Osaka Univ.)
13:30 - 14:45 |
| (1) |
13:30-13:55 |
Memory Assignment Method for Matrix Processing Array |
Akira Kobashi, Ittetsu Taniguchi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.), Kiyoshi Nakata (Renesas) |
| (2) |
13:55-14:20 |
Heuristic Instruction Scheduling Method for Processors with Partial Data Forwarding Structure |
Takuji Hieda, Hiroaki Tanaka, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) |
| (3) |
14:20-14:45 |
Reconfigurable Architecture with Caluculation Function for Shift Keying |
Ayataka Kobayashi, Ittetsu Taniguchi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) |
| |
14:45-14:55 |
Break ( 10 min. ) |
Thu, May 10 PM
Chair: Tohru Ishihara (Kyushu Univ.)
14:55 - 15:45 |
| (4) |
14:55-15:20 |
A Modeling of Dynamically Reconfigurable Processor using SystemC |
Kouji Ueda, Junji Kitamichi, Kenichi Kuroda (The Univ. of Aidu) |
| (5) |
15:20-15:45 |
An Architecture Design and its Evaluation for Speech Recognition System |
Joh Hashimato, Makoto Saitsuji, Takashi Kambe (Kinki Univ.) |
| |
15:45-16:00 |
Break ( 15 min. ) |
Thu, May 10 PM
16:00 - 17:00 |
| (6) |
16:00-17:00 |
[Panel Discussion]
Highlevel synthesis; will it be useful or useless? |
Masahiro Fukui (Ritsumeikan Univ.), Nagisa Ishiura (Kwansei Gakuin Univ.), Tomonori Izumi (Ritsumeikan Univ.), Akihisa Yamada (SHARP) |
Fri, May 11 AM
09:30 - 10:45 |
| (7) |
09:30-09:55 |
Automatic Generation of a Verification Environment for Hardware Units
-- Application to a Bus Bridge Design -- |
Rafael Kazumiti Morizawa, Hiroaki Iwashita, Koichiro Takayama (Fujitsu Labs.) |
| (8) |
09:55-10:20 |
On a lower bound for DAG covering problem and its application to an exact algorithm |
Yusuke Matsunaga (Kyushu Univ.) |
| (9) |
10:20-10:45 |
A Clock Deskew Method using PDE with Discrete Delay |
Yuko Hashizume, Naoki Otani, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC) |
| |
10:45-10:55 |
Break ( 10 min. ) |
Fri, May 11 AM
10:55 - 12:10 |
| (10) |
10:55-11:20 |
An Asynchronous Single-precision Floating-point Divider and its Implementation on FPGA |
Masayuki Hiromoto, Atsuko Takahashi, Shin'ichi Kouyama, Hiroyuki Ochi (Kyoto Univ.), Yukihiro Nakamura (Ritsumeikan Univ.) |
| (11) |
11:20-11:45 |
An SIMD MSD Multiplier based on variable GF($2^m$) for Elliptic Curve Cryptosystem |
Ryuta Nara, Kazunori Shimizu, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) |
| (12) |
11:45-12:10 |
On power-conscious approach for prefix graph synthesis |
Taeko Matsunaga (Waseda Univ), Yusuke Matsunaga (Kyushu Univ.) |
| |
12:10-13:20 |
Lunch Break ( 70 min. ) |
Fri, May 11 PM
13:20 - 15:00 |
| (13) |
13:20-13:45 |
A Flexible Power and Task Modeling for LSI Blocks |
Tatsuya Koyagi, Masahiro Fukui (Ritsumeikan Univ.), Resve Saleh (Univ. of British Columbia) |
| (14) |
13:45-14:10 |
A fast maximum delay estimation method for specified yield by statistical static timing analysis. |
Hiroki Furuya, Yukihide Kohira, Atsushi Takahashi (Tokyo Tech) |
| (15) |
14:10-14:35 |
An algorithm of power grid optimization for high-level floorplan |
Takayuki Hayashi, Yoshiyuki Kawakami, Masahiro Fukui (Ritsumeikan Univ.) |
| (16) |
14:35-15:00 |
Effect of Dummy Fill on High-Frequency Characteristics of On-Chip Interconnects |
Akira Tsuchiya, Hidetoshi Onodera (Kyoto Univ.) |
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