Tue, Jan 26 AM Development Environment 09:00 - 10:40 |
(1) RECONF |
09:00-09:25 |
A study of software development environment for dynamic-reconfigurable processor MuCCRA-3. |
Kazuei Hironaka, Katsunobu Nishimura (Tokai Univ.), Hideharu Amano (Keio Univ.) |
(2) RECONF |
09:25-09:50 |
Reducing scheduling overheads in Dynamically Reconfigurable Processors |
Ratna Krishnamoorthy (Univ of Tokyo), Keshavan Varadarajan, Mythri Alle (IISc), Ranjani Narayan (Morphing Machines), Masahiro Fujita (Univ of Tokyo), S K Nandy (IISc) |
(3) VLD |
09:50-10:15 |
Evaluation of Hardware/Software Partitioning Method with Consideration of Software Parallelization |
Junya Matsunaga, Michiaki Muraoka (Kochi Univ.), Dai Araki (InterDesign Technologies, Inc.) |
(4) RECONF |
10:15-10:40 |
Evaluation using Applications for RC-OS which supports Reconfigurable Computer System |
Kazuya Tokunaga, Akira Kojima, Tetsuo Hironaka (Hiroshima City Univ) |
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10:40-10:50 |
Break ( 10 min. ) |
Tue, Jan 26 AM Network 10:50 - 11:40 |
(5) RECONF |
10:50-11:15 |
A network deliverable hw/sw complex, video codec |
Ryosuke Kurogi, Kentaro Hanai, Hakaru Tamukoh, Yuuichi Kobayashi, Masatoshi Sekine (Tokyo Univ. of Agr and Tech.) |
(6) RECONF |
11:15-11:40 |
Development of Interdisciplinary Research Environment by Collaboration of e-Learning and Remote FPGA |
Jaeseong Kim, Shingo Yoshizawa, Yusaku Kaneta, Shin-ichi Minato, Hiroki Arimura, Yoshikazu Miyanaga (Hokkaido Univ.) |
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11:40-13:05 |
Lunch Break ( 85 min. ) |
Tue, Jan 26 PM Application 1 13:05 - 14:20 |
(7) RECONF |
13:05-13:30 |
FPGA Implementation of Discrete Wavlet Transform Using Impulse C |
Takaaki Miyajima (Keio Univ.), Masatoshi Arai (Calsonic Kansei), Hideharu Amano (Keio Univ.) |
(8) RECONF |
13:30-13:55 |
An FPGA Implementation of Array Processor Performing 3D-DCT Effectively |
Yuki Ikegaki, Hiroyuki Igarashi, Toshiaki Miyazaki, Stanislav G. Sedukhin (Univ. of Aizu) |
(9) RECONF |
13:55-14:20 |
Computer Aided Detection System Implementation for recognize cancer in Mammograms over a FPGA |
Yessica Suarez Henandez (IPN/Univ. of Electro-Comm.), Sayaka Akioka, Tsutomu Yoshinaga, Volodymyr Ponomaryov, Gonzalo Duchen Sanchez (Univ. of Electro-Comm.) |
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14:20-14:30 |
Break ( 10 min. ) |
Tue, Jan 26 PM Bus and Interconnect Architecture 14:30 - 15:45 |
(10) CPSY |
14:30-14:55 |
A Non-Minimal Fully Adaptive Routing Using a Single-Flit Packet Structure |
Yuri Nishikawa (Keio Univ.), Michihiro Koibuchi (NII), Hiroki Matsutani (Tokyo Univ.), Hideharu Amano (Keio Univ.) |
(11) RECONF |
14:55-15:20 |
Design of Reconfigurable Logic Device based on Variable Grain Logic Cell |
Kazuki Inoue, Yasuhiro Okamoto, Qian Zhao, Komei Yoshizawa, Hiroki Yosho, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
(12) |
15:20-15:45 |
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15:45-15:55 |
Break ( 10 min. ) |
Tue, Jan 26 PM Datapath Optimization 15:55 - 17:35 |
(13) VLD |
15:55-16:20 |
Residue-Binary Conversion Using Signed-Digit Number Arithmetic |
Changjun Jiang, Shugang Wei (Gunma Univ.) |
(14) VLD |
16:20-16:45 |
Implementation Method and Performance Evaluation of Residue Arithmetic Circuits Using Signed-Digit Number Representation |
Mingda Zhang, Shugang Wei (Gunma Univ.) |
(15) RECONF |
16:45-17:10 |
Hardware Specialization of Digital Filters for Vibration Control |
Yasuaki Tezuka, Shuichi Ichikawa, Yoshiyuki Noda (Toyohashi Univ. of Tech.) |
(16) VLD |
17:10-17:35 |
A Dedicated Functional Unit Synthesis Algorithm with MISO Structures based on Partial Matching |
Norihiro Hashimoto, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) |
Wed, Jan 27 AM Low-power Design 09:00 - 09:50 |
(17) RECONF |
09:00-09:25 |
Architecture of a Low-Power FPGA Based on Self-Adaptive Voltage Control |
Shota Ishihara, Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) |
(18) RECONF |
09:25-09:50 |
Implementation of Power Reduction with Dynamically Dual-VDD Assignment to Dynamically Reconfigurable Processors Array |
Yusuke Umahashi (Shibaura Inst. of Tech.), Toru Sano (Keio Univ.), Satoshi Koyama (Shibaura Inst. of Tech.), Yoshiki Saito, Hideharu Amano (Keio Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech.) |
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09:50-10:00 |
Break ( 10 min. ) |
Wed, Jan 27 AM Acceleration Techniques 10:00 - 11:40 |
(19) CPSY |
10:00-10:25 |
Granularity Optimization Method for AES Encryption Implementation on CUDA |
Naoki Nishikawa, Keisuke Iwai, Takakazu Kurokawa (NDA) |
(20) RECONF |
10:25-10:50 |
Effective Hardware Task Context Switching in Virtex-4 FPGAs |
Krzysztof Jozwik, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada (Nagoya Univ.) |
(21) RECONF |
10:50-11:15 |
Hardware Acceleration in a Scalable FPGA System |
Hironori Nakajo, Ryuichi Sakamoto (Tokyo Univ. of Agr and Tech.) |
(22) RECONF |
11:15-11:40 |
Expansion of Hardware in a Scalable FPGA System |
Hironori Nakajo (Tokyo Univ. of Agr and Tech.), Takefumi Miyoshi (Tokyo Inst. of Tech.), Satoshi Funada (e-trees.Japan, Inc), Ryuichi Sakamoto (Tokyo Univ. of Agr and Tech.) |
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11:40-12:40 |
Lunch Break ( 60 min. ) |
Wed, Jan 27 PM Application 2 12:40 - 13:55 |
(23) RECONF |
12:40-13:05 |
An efficient hardware-oriented algorithm for regular expression matching based on parallel bit-distribution |
Yusaku Kaneta, Shingo Yoshizawa, Shin-ichi Minato, Hiroki Arimura, Yoshikazu Miyanaga (Hokkaido Univ.) |
(24) RECONF |
13:05-13:30 |
Regular Expression Pattern Matching Hardware for Realizing Iteration of Strings Using Quantifiers |
Yoichi Wakaba, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi (Hiroshima City Univ) |
(25) RECONF |
13:30-13:55 |
A Packet Classifier Using a Parallel Branching Program Machine |
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.), Yoshifumi Kawamura (Renesas Tech Corp.) |
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13:55-14:05 |
Break ( 10 min. ) |
Wed, Jan 27 PM Dependable Design 14:05 - 15:20 |
(26) RECONF |
14:05-14:30 |
An Implementation of Fail-soft Systems with Adaptive Fault Tolerance using SRAM-based FPGAs |
Satoshi Fujie, Ryoji Noji, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) |
(27) RECONF |
14:30-14:55 |
Fault Recovery Technique for Softcore Processor using Partial Reconfiguration |
Yoshihiro Ichinomiya, Shiro Tanoue, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
(28) VLD |
14:55-15:20 |
An Estimation Method of Delay Time Variation by Crosstalk in Logic Circuit Level |
Masayuki Kobayashi, Wataru Sento, Masahiko Toyonaga, Michiaki Muraoka (Kochi Univ.) |
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15:20-15:30 |
Break ( 10 min. ) |
Wed, Jan 27 PM Optically Reconfigurable Architecture 15:30 - 16:45 |
(29) RECONF |
15:30-15:55 |
A remote dynamic optically reconfigurable gate array using a fiber array |
Yumiko Ueno, Minoru Watanabe (Shizuoka Univ.) |
(30) RECONF |
15:55-16:20 |
Compensation method for photodiode characteristics variation using an analog configuration context |
Yuji Aoyama, Minoru Watanabe (Shizuoka Univ.) |
(31) RECONF |
16:20-16:45 |
A programmable optically reconfigurable gate array with a silver-halide holographic memory |
Shinya Kubota, Minoru Watanabe (Shizuoka Univ.) |