Tue, Jan 13 AM 09:20 - 09:30 |
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09:20-09:30 |
Opening Address ( 10 min. ) |
Tue, Jan 13 AM 09:30 - 10:30 |
(1) |
09:30-10:00 |
Evalutions of Prediction Router for Low-Latency On-Chip Networks |
Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (National Inst. of Info.The Univ), Hideharu Amano (Keio Univ.), Tsutomu Yoshinaga (The Univ. of Electro-Communications) |
(2) |
10:00-10:30 |
A 820 Mb/s Baseband Processor LSI based on LDPC Coded OFDM for UWB systems |
Shinsuke Ushiki, Koichi Nakamura, Kazunori Shimizu, Qi Wang, Yuta Abe, Satoshi Goto, Takeshi Ikenaga (Waseda Univ.) |
Tue, Jan 13 10:30 - 12:30 |
(3) |
10:30-11:30 |
[Invited Talk]
Evolution of application processor OMAP for mobile products |
Masahiro Miyazaki (Texas Inst. Japan Limited) |
(4) |
11:30-12:30 |
[Invited Talk]
How and What to create and build up software for digital consumer electronics |
Kazuo Kajimoto (Panasonic) |
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12:30-13:30 |
Lunch Break ( 60 min. ) |
Tue, Jan 13 PM 13:30 - 15:30 |
(5) |
13:30-14:30 |
[Invited Talk]
Trends of automotive software platform |
Akihito Iwai (DENSO) |
(6) |
14:30-15:30 |
[Invited Talk]
Customizable Dataplane Processors for System-on-Chip |
Takayuki Sugawara (Tensilica K.K.) |
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15:30-15:45 |
Break ( 15 min. ) |
Tue, Jan 13 PM 15:45 - 17:45 |
(7) |
15:45-17:45 |
[Panel Discussion]
Past and Future of Platform-based Designs |
Kazuaki Murakami (Kyushu Univ.), Akihito Iwai (DENSO), Kazuo Kajimoto (Panasonic), Takayuki Sugawara (Tensilica K.K.), Masahiro Miyazaki (Texas Inst. Japan Limited) |
Wed, Jan 14 AM 09:00 - 10:30 |
(8) |
09:00-09:30 |
The Task Design by using of LTSA and SPIN |
Toshiyuki Fujikura (eSOL), Akira Nonaka (Tao Bears), Masanori Usami (eSOL) |
(9) |
09:30-10:00 |
Object-Oriented Programming and Testing Environment for an FPGA Using CORBA/GIOP Protocol |
Takeshi Ohkawa, Kenji Toda (AIST/ITRI) |
(10) |
10:00-10:30 |
A Low-Power Feild-Programmable VLSI Based on Autonomous Fine-Grain Power-Gating |
Masanori Hariyama, Shota Ishihara, Michitaka Kameyama (Tohoku Univ.) |
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10:30-10:45 |
Break ( 15 min. ) |
Wed, Jan 14 AM 10:45 - 12:15 |
(11) |
10:45-11:15 |
Evaluation of a Heterogeneous Multi-Core Architecture for Multimedia Applications |
Daisuke Okumura, Hasitha Muthumala Waidyasooriya, Takehisa Matsuda, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) |
(12) |
11:15-11:45 |
Performance Evaluation of Parallelizing Compiler Cooperated Heterogeneous Multicore Architecture Using Media Applications |
Teruo Kamiyama, Yasutaka Wada, Akihiro Hayashi, Masayoshi Mase, Hirofumi Nakano, Takeshi Watanabe, Keiji Kimura, Hironori Kasahara (Waseda Univ.) |
(13) |
11:45-12:15 |
Local Memory Management Scheme by a Compiler for Multicore Processor |
Taku Momozono, Hirofumi Nakano, Masayoshi Mase, Keiji Kimura, Hironori Kasahara (Waseda Univ.) |
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12:15-13:15 |
Lunch Break ( 60 min. ) |
Wed, Jan 14 PM 13:15 - 15:15 |
(14) |
13:15-13:45 |
Feasibility of an Embedded Virtual Machine under Parallel or Distributed Processing Environment |
Hirofumi Yano, Masaki Nakanishi, Shinobu Miwa, Hironori Nakajo (Tokyo Univ. of Agriculture and Tech.) |
(15) |
13:45-14:15 |
Fine-Grained Dynamic Sleep Control on the Combination of High-Perfomance Cores and Low-Power Cores |
Naomi Seki, Lei Zhao, Daisuke Ikebuchi, Yu Kojima, Hideharu Amano (Keio Univ) |
(16) |
14:15-14:45 |
Power Saving with Asynchronous Remote Procedure Call for Embedded Multi-core Processor |
Hiromasa Yamauchi, Takahisa Suzuki, Makiko Ito (Fujitsu Lab Ltd.,) |
(17) |
14:45-15:15 |
A Power Saving Scheme on Multicore Processors Using OSCAR API |
Ryo Nakagawa, Masayoshi Mase, Jun Shirako, Keiji Kimura, Hironori Kasahara (Waseda Univ.) |
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15:15-15:30 |
Break ( 15 min. ) |
Wed, Jan 14 PM 15:30 - 17:30 |
(18) |
15:30-16:00 |
Predicting Cache Miss Rates via Simulation Results Reuse |
Takatsugu Ono, Koji Inoue, Kazuaki Murakami (Kyushu Univ.), Koji Kai (Panasonic) |
(19) |
16:00-16:30 |
The Cache-Core optimization on Multi-CoreProcessors considering several overheads |
Yosuke Mori, Akira Moriya, Naoki Fujieda, Kenji Kise (Tokyo Inst. of Tech.) |
(20) |
16:30-17:00 |
A Low-Power Full-HD H.264 High-Profile Codec Based on a Heterogeneous Multiprocessor Architecture |
Kenichi Iwata, Seiji Mochizuki, Motoki Kimura, Tetsuya Shibayama, Fumitaka Izuhara, Hiroshi Ueda (Renesas Tech Corp.), Koji Hosogi, Hiroaki Nakata, Masakazu Ehama (Hitachi Ltd.), Toru Kengaku, Takuichiro Nakazawa, Hiromi Watanabe (Renesas Tech Corp.) |
(21) |
17:00-17:30 |
An H.264/AVC High422 Profile and MPEG-2 422 Profile Encoder LSI for HDTV Broadcasting Infrastructures |
Koyo Nitta (NTT), Mitsuo Ikeda (NEL), Hiroe Iwasaki, Takayuki Onishi, Takashi Sano, Atsushi Sagata, Yasuyuki Nakajima (NTT), Minoru Inamori (NEL), Takeshi Yoshitome (NTT), Hiroaki Matsuda (NEL), Ryuichi Tanida, Atsushi Shimizu, Ken Nakamura, Jiro Naganuma (NTT) |