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=============================================== Technical Committee on Reconfigurable Systems (RECONF) Chair: Yuichiro Shibata (Nagasaki Univ.) Vice Chair: Kentaro Sano (RIKEN), Yoshiki Yamaguchi (Tsukuba Univ.) Secretary: Takefumi Miyoshi (e-trees.Japan), Yuuki Kobayashi (NEC) Assistant: Hiroki Nakahara (Tokyo Inst. of Tech.), Yukitaka Takemura (INTEL) =============================================== Technical Committee on VLSI Design Technologies (VLD) Chair: Daisuke Fukuda (Fujitsu Labs.) Vice Chair: Kazutoshi Kobayashi (Kyoto Inst. of Tech.) Secretary: Yuichi Sakurai (Hitachi), Daisuke Kanemoto (Osaka Univ.) Assistant: Takuma Nishimoto (Hitachi) =============================================== Technical Committee on Computer Systems (CPSY) Chair: Hidetsugu Irie (Univ. of Tokyo) Vice Chair: Michihiro Koibuchi (NII), Kota Nakajima (Fujitsu Lab.) Secretary: Shinya Takameda (Hokkaido Univ.), Tomoaki Tsumura (Nagoya Inst. of Tech.) Assistant: Shugo Ogawa (Hitachi), Eiji Arima (Univ. of Tokyo) =============================================== Special Interest Group on System Architecture (IPSJ-ARC) Chair: Hiroshi Inoue (Kyushu Univ.) Secretary: Satoshi Imamura (Fujitsu lab.), Ryota Shioya (Nagoya Univ.), Teruo Tanimoto (Kyushu Univ.), Koyo Nitta (NTT) =============================================== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) Chair: Yuichi Nakamura (NEC) Secretary: Kenshu Seto (Tokyo City Univ.), Yukio Mitsuyama (Kochi Univ. of Tech.), Kazuki Oya (Mitsubishi Electric), Masayuki Hiromoto (Fujistu Lab.) DATE: Mon, Jan 25, 2021 09:00 - 18:00 Tue, Jan 26, 2021 09:00 - 17:25 PLACE: TOPICS: FPGA Applications, etc. ---------------------------------------- Mon, Jan 25 AM HPC (09:00 - 10:40) ---------------------------------------- (1)/CPSY 09:00 - 09:25 (See Japanese page.) (2)/RECONF 09:25 - 09:50 (See Japanese page.) (3)/RECONF 09:50 - 10:15 Study on Design and Evaluation of Stream Processing Hardware for Sound Simulation by FDTD method Hiroki Tada (JAIST), Tomohiro Ueno, Atsushi Koshiba, Kentaro Sano (R-CCS), Ryuta Kawano, Yasushi Inoguchi (JAIST) (4)/RECONF 10:15 - 10:40 An implementation and evaluation of Fast Fourier Transform on FPGA for High-performance Computing Takaaki Miyajima, Tomohiro Ueno, Kentaro Sano (RIKEN) ----- Break ( 15 min. ) ----- ---------------------------------------- Mon, Jan 25 AM (10:55 - 11:55) ---------------------------------------- (5)/CPSY 10:55 - 11:55 [Invited Talk] System Architecture and Interconnect Development for the Supercomputer "K" and "Fugaku" Yuichiro Ajima (Fujitsu) ----- Break ( 60 min. ) ----- ---------------------------------------- Mon, Jan 25 PM (12:55 - 14:10) ---------------------------------------- (6)/CPSY 12:55 - 13:20 (See Japanese page.) (7)/CPSY 13:20 - 13:45 (See Japanese page.) (8)/CPSY 13:45 - 14:10 Throughput improvement of Responsive Link with High Speed Transceiver in FPGA Masahiko Takahashi, Yamasaki Nobuyuki (Keio Univ.) ----- Break ( 15 min. ) ----- ---------------------------------------- Mon, Jan 25 PM (14:25 - 16:05) ---------------------------------------- (9)/CPSY 14:25 - 14:50 Evaluations of FPGA-based Neural Networks using of ODE Hirohisa Watanabe, Hiroki Matsutani (Keio Univ.) (10)/RECONF 14:50 - 15:15 Efficient Attention Mechanism by Softmax Function with Trained Coefficient Kaito Hirota (UT), O'uchi Shinichi (AIST), Fujita Masahiro (UT) (11)/RECONF 15:15 - 15:40 A High-speed Convolutional Neural Network Accelerator for an Adaptive Resolution on an FPGA Koki Sayama, Akira Jinguji, Naoto Soga, Hiroki Nakahara (Tokyo Tech) (12)/RECONF 15:40 - 16:05 Implementation of Quantized Deep Neural Network on FPGA Pan Hongyi (AIST/The Univ. of Tokyo), Ben Ahmed Akram, Ikegami Tsutomu (AIST), Tominaga Kazuki (The Univ. of Tokyo), Kudoh Tomohiro (AIST/The Univ. of Tokyo) ----- Break ( 15 min. ) ----- ---------------------------------------- Mon, Jan 25 PM (16:20 - 18:00) ---------------------------------------- (13)/VLD 16:20 - 16:45 Residual signed-digit number - residual binary number conversion algorithm Yuki Saba, Yuuki Tanaka, Shugang Wei (Gunma Univ.) (14)/VLD 16:45 - 17:10 Comparison of ICA Algorithms in the Compressed Sensing EEG Measurement Framework Using OD-ICA Wataru Okumura, Daisuke Kanemoto, Osamu Maida, Tetsuya Hirose (Osaka Univ) (15)/VLD 17:10 - 17:35 Low Power EEG Measurement Using Compressed Sensing Consideration of the Sampling Interval Yuki Okabe, Daisuke Kanemoto (Osaka Univ.), Tomoya Mochizuki (Yamanashi Univ.), Osamu Maida, Tetsuya Hirose (Osaka Univ.) (16)/VLD 17:35 - 18:00 High speed architectures of decimal counters Shuhei Yanagawa, Yuuki Tanaka, Shugang Wei (Gunma Univ.) ----- Break ( 30 min. ) ----- ----- Social Event ( 120 min. ) ----- ---------------------------------------- Tue, Jan 26 AM (09:00 - 10:15) ---------------------------------------- (17)/CPSY 09:00 - 09:25 Acceleration of Database Query Processing Using FPGA Hirohiko Ozaku (UEC), Masato Yoshimi (TIS), Celimuge Wu, Tsutomu Yoshinaga (UEC) (18)/RECONF 09:25 - 09:50 FPGA Accelerator Design for Real-Time Object Detection Koichiro Ban, Masanori Furuta, Daisuke Kobayashi (Toshiba) (19)/RECONF 09:50 - 10:15 FPGA Implementation of Semantic Segmentation on LWIR Images for Autonomous Robot Yuichiro Niwa (ATLA), Taiki Fujii (eSOL) ----- Break ( 15 min. ) ----- ---------------------------------------- Tue, Jan 26 AM (10:30 - 11:45) ---------------------------------------- (20)/CPSY 10:30 - 10:55 (See Japanese page.) (21)/CPSY 10:55 - 11:20 Network Intrusion Detection System based on Hybrid FPGA/GPU Pattern Matching Shunta Kikuchi (AIST/The Univ. of Tokyo), Tsutomu Ikegami, Akram ben Ahmed (AIST), Tomohiro Kudoh (The Univ. of Tokyo/AIST), Ryohei Kobayashi, Norihisa Fujita, Taisuke Boku (Univ. of Tsukuba) (22)/RECONF 11:20 - 11:45 Hiroaki Suzuki (Keio Univ), Wataru Takahashi (NEC), Kazutoshi Wakabayashi (Tokyo Univ), Hideharu Amano (Keio Univ) ----- Break ( 60 min. ) ----- ---------------------------------------- Tue, Jan 26 PM (12:45 - 14:00) ---------------------------------------- (23)/RECONF 12:45 - 13:10 SLM based FPGA-IP soft core Yuya Nakazato, Hiroaki Koga (Kumamoto Univ.), Zhao Qian (KIT), Motoki Amagasaki, Morihiro Kuga, Masahiro Iida (Kumamoto Univ.) (24)/RECONF 13:10 - 13:35 Automated architecture exploration on Scala-based hardware development environment Ryota Yamashita, Daichi Teruya, Hironori Nakajo (TUAT) (25) 13:35 - 14:00 ----- Break ( 15 min. ) ----- ---------------------------------------- Tue, Jan 26 PM (14:15 - 15:55) ---------------------------------------- (26)/VLD 14:15 - 14:40 A new method for evaluating corruption metric and resilience of logic locking Shusaku Minami, Yusuke Matsunaga (Kyushu Univ.) (27)/VLD 14:40 - 15:05 Mutation-Based Fuzzing Using Data Structure Captured via Data Generator Noriyuki Namba, Nagisa Ishiura (Kwansei Gakuin Univ.) (28)/VLD 15:05 - 15:30 Detection of Vulnerability Inducing Code Optimization Based on Binary Code Yuka Azuma, Nagisa Ishiura (Kwansei Gakuin Univ.) (29)/VLD 15:30 - 15:55 Performance Testing of VRP Optimization of C Compilers by Random Program Generation Daiki Murakami, Nagisa Ishiura (Kwansei Gakuin Univ.) ----- Break ( 15 min. ) ----- ---------------------------------------- Tue, Jan 26 PM (16:10 - 17:25) ---------------------------------------- (30) 16:10 - 16:35 (31) 16:35 - 17:00 (32) 17:00 - 17:25 # Information for speakers General Talk will have 20 minutes for presentation and 5 minutes for discussion. === Technical Committee on Reconfigurable Systems (RECONF) === # SECRETARY: Yuichiro Shibata（Nagasaki Univ.） E-mail:  ba  cis     -u # ANNOUNCEMENT: # http://www.ieice.org/~reconf/ === Technical Committee on VLSI Design Technologies (VLD) === # FUTURE SCHEDULE: Wed, Mar 3, 2021 - Thu, Mar 4, 2021: Online [Mon, Jan 18], Topics: Design Technology for System-on-Silicon, Hardware Security, etc. # SECRETARY: Yuichi SAKURAI (Hitachi) E-mail:  i   ixj  # ANNOUNCEMENT: # See also VLD's homepage: http://www.ieice.org/~vld/ === Technical Committee on Computer Systems (CPSY) === # FUTURE SCHEDULE: Thu, Mar 25, 2021 - Fri, Mar 26, 2021: Online [Wed, Jan 20], Topics: ETNET2021 # SECRETARY: CPSY WEB https://www.ieice.org/~cpsy/ === Special Interest Group on System Architecture (IPSJ-ARC) === # FUTURE SCHEDULE: Thu, Mar 25, 2021 - Fri, Mar 26, 2021: Online [Wed, Jan 20], Topics: ETNET2021 === Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) === # FUTURE SCHEDULE: Thu, Mar 25, 2021 - Fri, Mar 26, 2021: Online [Wed, Jan 20], Topics: ETNET2021 # SECRETARY: Kenshu Seto (Tokyo City University) E-mail: k   tcu# ANNOUNCEMENT: # Please see the IPSJ-SLDM page below: http://www.sig-sldm.org/ Last modified: 2020-12-22 13:41:56 |
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