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| Chair |
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Shigeyoshi Watanabe (Shonan Inst. of Tech.) |
| Vice Chair |
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Toshihiro Sugii (Fujitsu Microelectronics) |
| Secretary |
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Hisahiro Anzai (Sony), Tetsuro Endo (Tohoku Univ.) |
| Assistant |
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Katsunori Onishi (Kyushu Inst. of Tech.), Yukinori Ono (NTT) |
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| Conference Date |
Fri, Feb 5, 2010 10:00 - 17:20 |
| Topics |
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| Conference Place |
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Fri, Feb 5 AM
10:00 - 17:20 |
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10:00-10:05 |
Opening ( 5 min. ) |
| (1) |
10:05-10:50 |
[Keynote Address]
Key Issues and Future Prospects for 3-D Integration Technology |
Mitsumasa Koyanagi, Takafumi Fukushima, Kangwook Lee, Tetsu Tanaka (Tohoku Univ.) |
| (2) |
10:50-11:20 |
Highly-Reliable Cu Interconnect covered with CoWB Metal-cap in a Waterproof Molecular-Pore-Stack (MPS)-SiOCH film |
Yoshihiro Hayashi, Masayoshi Tagami, Naoya Furutake, Naoya Inoue, Emiko Nakazawa, Kouji Arita (NEC Electronics) |
| (3) |
11:20-11:50 |
Feasibility Study of 70nm Pitch Cu/Porous Low-k D/D Integration Featuring EUV Lithography toward 22nm Generation |
Naofumi Nakamura, Noriaki Oda, Eiichi Soda, Nobuki Hosoi, Akifumi Gawase, Hajime Aoyama, Y. Tanaka, D. Kawamura, S. Chikaki, M. Shiohara, Nobuaki Tarumi, S. Kondo, Ichiro Mori, S. Saito (SELETE) |
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11:50-13:00 |
Break ( 70 min. ) |
| (4) |
13:00-13:30 |
Advanced Direct-CMP Process for Porous Low-k Thin Film |
Hayato Korogi (Panasonic), Hiroyuki Chibahara (Renesas), S. Suzuki, M. Tsutsue (Panasonic), K. Seo (Panasonic Semiconductor Engineering), Y. Oka, K. Goto, M. Akazaw, Hiroshi Miyatake (Renesas), S. Matsumoto, T. Ueda (Panasonic) |
| (5) |
13:30-14:00 |
Optimization of Metallization Processes for 32-nm node Highly Reliable Ultralow-k (k=2.4)/Cu Multilevel Interconnects Incorporating a Bilayer Low-k Barrier Cap (k=3.9) |
M. Iguchi, S. Yokogawa, Hirokazu Aizawa, Y. Kakuhara, Hideaki Tsuchiya, Norio Okada, Kiyotaka Imai, M. Tohara, K. Fujii (NEC Electronics), T. Watanabe (Toshiba) |
| (6) |
14:00-14:30 |
Low resistive and highly reliable copper interconnects in combination of silicide-cap with Ti-barrier for 32 nm-node and beyond |
Yumi Hayashi, Noriaki Matsunaga, Makoto Wada, Shinichi Nakao, Atsuko Sakata, Kei Watanabe, Hideki Shibata (Toshiba) |
| (7) |
14:30-15:00 |
Performance of Cu Dual-Damascene Interconnects Using a Thin Ti-Based Self-Formed Barrier Layer for 28-nm Node and Beyond |
K. Ohmori, K. Mori, K. Maekawa (Renesas), Kazuyuki Kohama, Kazuhiro Ito (Kyoto Univ.), T. Ohnishi, M. Mizuno (KOBE STEEL), K. Asai (Renesas), M. Murakami (Ritsumeikan Trust), Hiroshi Miyatake (Renesas) |
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15:00-15:15 |
Break ( 15 min. ) |
| (8) |
15:15-15:45 |
Chip-Level and Package-Level Seamless Interconnect Technologies for Advanced Packaging |
Shintaro Yamamichi, Kentaro Mori, Katsumi Kikuchi, Hideya Murai, D. Ohshima, Y. Nakashima (NEC), Kouji Soejima, Masaya Kawano (NEC Electronics), Tomoo Murakami (NEC) |
| (9) |
15:45-16:15 |
Defects in Cu/low-k Interconnects Probed Using Monoenergetic Positron Beams |
Akira Uedono (Tsukuba Univ.), Naoya Inoue, Y. Hayashi, K. Eguchi, T. Nakamura, Y. Hirose, Masaki Yoshimaru (STARC), Nagayasu Oshima, Toshiyuki Ohdaira, R. Suzuki (National Institute of Advanced Industrial Science and Technology) |
| (10) |
16:15-16:45 |
Evaluation of Dielectric Constant through Direct CMP of Porous Low-k Film |
Masako Kodera, T. Takahashi, G. Mimamihaba (Toshiba Corp.) |
| (11) |
16:45-17:15 |
Evaluation of Line-Edge Roughness in Cu/Low-k Interconnect Patterns |
Atsuko Yamaguchi, D. Ryuzaki, Kenichi Takeda (Hitachi), Hiroki Kawada (Hitachi High-Tech.) |
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17:15-17:20 |
Closing ( 5 min. ) |
| Announcement for Speakers |
| General Talk | Each speech will have 25 minutes for presentation and 5 minutes for discussion. |
| Keynote Address | Each speech will have 40 minutes for presentation and 5 minutes for discussion. |
| Contact Address and Latest Schedule Information |
| SDM |
Technical Committee on Silicon Device and Materials (SDM) [Latest Schedule]
|
| Contact Address |
Hisahiro Ansai(Sony)
Tel 046-201-3297 Fax046-202-6572
E- : Hi    Ani   ny |
Last modified: 2009-12-17 00:36:25
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