Mon, Jan 23 PM
13:00 - 14:15 |
(1)
RECONF |
13:00-13:25 |
A Hardware Acceleration of Template Matching using FPGA and MPU |
Yuji Matumoto, Youichi Tomioka, Junji Kitamichi (The University of Aizu) |
(2)
RECONF |
13:25-13:50 |
Optimal Design of FIR filter using a Real Coded Genetic Algorithm Processor |
Akihiko Tsukahara, Akinori Kanasugi (Tokyo Denki Univ.) |
(3)
RECONF |
13:50-14:15 |
GRAPE9-MPX: development of an accelerator system dedicated for multi-precision arithmetic operations and its application |
Hiroshi Daisaka (Hitotsubashi Univ.), Naohito Nakasato (Univ. of Aizu), Tadashi Ishikawa, Fukuko Yuasa (KEK), Keigo Nitadori (RIKEN/AICS) |
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14:15-14:30 |
Break ( 15 min. ) |
Mon, Jan 23 PM
14:30 - 16:10 |
(4)
RECONF |
14:30-14:55 |
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(5)
RECONF |
14:55-15:20 |
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(6)
RECONF |
15:20-15:45 |
Implementation of Multiple FPGAs with High Speed Serial Optical Interconnection |
Futoshi Murase, Daichi Takagi, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ) |
(7)
CPSY |
15:45-16:10 |
Distributed Handshake-Join Processing for Stream Data on Multiple FPGA Nodes |
Kousuke Tada, Naoto Kawahara, Masato Yoshimi, Celimuge, Wu., Tsutomu Yoshinaga (UEC) |
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16:10-16:25 |
Break ( 15 min. ) |
Mon, Jan 23 PM
16:25 - 17:40 |
(8)
CPSY |
16:25-16:50 |
A Case for FPGA Based 10GbE Switch Aggregating Computation Results of GPUs |
Kazuma Takemoto, Ami Hayashi, Shin Morishima, Hiroki Matsutani (Keio Univ.) |
(9)
CPSY |
16:50-17:15 |
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(10)
RECONF |
17:15-17:40 |
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Kazusa Musha (Keio Univ.), Tomohiro Kudoh (Tokyo Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) |
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18:00-20:00 |
Social ( 120 min. ) |
Tue, Jan 24 AM
09:00 - 10:40 |
(11)
RECONF |
09:00-09:25 |
Overview of an HLS Framework Surpporting IoT/CPS Development |
Daichi Teruya, Hironori Nakajo (TUAT) |
(12)
RECONF |
09:25-09:50 |
Framework for a Hybrid System with a pair of MCU and FPGA |
Ryota Suzuki, Nakajo Hironori (TUAT) |
| (13) |
09:50-10:15 |
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| (14) |
10:15-10:40 |
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10:40-10:55 |
Break ( 15 min. ) |
Tue, Jan 24 AM
10:55 - 12:10 |
(15)
CPSY |
10:55-11:20 |
A Case for Remote GPU Assignment for VR Applications |
Shin Morishima, Masahiro Okazaki (Keio Univ.), Hiroki Matsutani (Keio Univ.PRESTO/NII) |
(16)
CPSY |
11:20-11:45 |
Evaluation of the PEACH3 used for communication in application |
Takahiro Kaneda (Keio Univ.), Toshihiro Hanawa (UTokyo), Hideharu Amano (Keio Univ.) |
(17)
CPSY |
11:45-12:10 |
Optimization of Fresnel hologram computation on GPU using decomposition method |
Shinpei Watanabe (Utsunomiya Univ.), Boaz Jessie Jackin (NICT), Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota, Yoshio Hayasaki, Toyohiko Yatagai, Takanobu Baba (Utsunomiya Univ.) |
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12:10-13:30 |
Lunch ( 80 min. ) |
Tue, Jan 24 PM
13:30 - 15:10 |
(18)
CPSY |
13:30-13:55 |
Implementation of Path Profiler Using Loop Block for Dynamic Behavior Analysis of Nested Loops |
Yuki Kikuchi, Kanemitsu Ootsu, Takanobu Baba, Takashi Yokota, Takeshi Ohkawa (Utsunomiya Univ.) |
(19)
CPSY |
13:55-14:20 |
Expression of Positional registers for Tamper resistance |
Kiyohiro Sato, Naoki Fujieda, Shuichi Ichikawa (TUT) |
(20)
RECONF |
14:20-14:45 |
Proposal of Processor Enabling to Start-Up Internal Modules Distributed Energy Consumption |
Hiroaki Kaneko, Akinori Kanasugi (Tokyo Denki Univ.) |
| (21) |
14:45-15:10 |
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15:10-15:25 |
Break ( 15 min. ) |
Tue, Jan 24 PM
15:25 - 16:40 |
(22)
RECONF |
15:25-15:50 |
Implementation of Binarized Deep Neural Network for FPGA Considering Power Performance Enhancement |
Haruyoshi Yonekawa, Hiroki Nakahara (Tokyo Tech), Masato Motomura (Hokkaido Univ.) |
(23)
RECONF |
15:50-16:15 |
A Memory Reduction with Neuron Pruning for a Convolutional Neural Network: Its FPGA Realization |
Tomoya Fujii, Simpei Sato, Hiroki Nakahara (Tokyo Tech), Masato Motomura (Hokkaido univ.) |
(24)
RECONF |
16:15-16:40 |
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16:40-16:55 |
Break ( 15 min. ) |
Tue, Jan 24 PM
16:55 - 18:10 |
(25)
RECONF |
16:55-17:20 |
FPGA Implementation of Mahalanobis Distance-Based Outlier Detection for Streaming Data |
Yuto Arai, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi (Hiroshima City Univ.) |
(26)
VLD |
17:20-17:45 |
A New Residue Addition Algorithm Using Signed-Digit Numbers and Its Application to RSA Encryption |
Kazumasa Ishikawa, Yuuki Tanaka, Shugang Wei (Gunma Univ.) |
(27)
RECONF |
17:45-18:10 |
Trace-Driven Emulation of Large-Scale Networks-on-Chip on FPGAs |
Thiem Van Chu, Kenji Kise (Tokyo Tech) |
Wed, Jan 25 AM
09:00 - 10:40 |
(28)
CPSY |
09:00-09:25 |
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(29)
VLD |
09:25-09:50 |
Investigation of the influence of input sequences on the calculation accuracy in an approximate operation using a typical circuit |
Shimpei Sato, Yuta Ukon, Atsushi Takahashi (Tokyo TECH) |
(30)
VLD |
09:50-10:15 |
Finite state machine design for high accurate stochastic computing |
Masashi Tawada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) |
(31)
VLD |
10:15-10:40 |
MTJ-based Nonvolatile Flip-Flop Circuit Enabling to Verify Stored Data |
Junya Akaike, Kimiyoshi Usami (SIT) |
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10:40-10:55 |
Break ( 15 min. ) |
Wed, Jan 25 AM
10:55 - 12:35 |
(32)
VLD |
10:55-11:20 |
Thermal transient analysis and evaluation of three-dimensional stacked chips |
Shogo Yasuda, Kimiyoshi Usami (SIT) |
| (33) |
11:20-11:45 |
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| (34) |
11:45-12:10 |
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| (35) |
12:10-12:35 |
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12:35-14:00 |
Lunch ( 85 min. ) |
Wed, Jan 25 PM
14:00 - 15:15 |
(36)
CPSY |
14:00-14:25 |
An FPGA NIC Based Distributed Ledger Caching for Blockchain |
Yuma Sakakibara, Kohei Nakamura (Keio Univ.), Hiroki Matsutani (Keio Univ./PRESTO/NII) |
(37)
CPSY |
14:25-14:50 |
Proxy Responses for MapReduce Delayed Task Using 10GbE FPGA Switch |
Koya Mitsuzuka, Ami Hayashi (Keio Univ.), Hiroki Matsutani (Keio Univ./PRESTO/NII) |
(38)
CPSY |
14:50-15:15 |
Design and Evaluation of A Suboptimal Unidirectional Network |
Tomohiro Totoki, Hiroshi Nakahara, Daichi Fujiki (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) |
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