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=============================================== Technical Committee on VLSI Design Technologies (VLD) Chair: Makoto Ikeda (Univ. of Tokyo) Vice Chair: Toshiyuki Shibuya (Fujitsu Labs.) Secretary: Shigetoshi Nakatake (Univ. of Kitakyushu), Noriyuki Minegishi (Mitsubishi Electric) =============================================== Technical Committee on Integrated Circuits and Devices (ICD) Chair: Takeshi Yamamura (Fujitsu Labs.) Vice Chair: Minoru Fujishima (Hiroshima Univ.) Secretary: Toshimasa Matsuoka (Osaka Univ.), Osamu Watanabe (Toshiba) Assistant: Shinichi Ouchi (AIST), Takeshi Yoshida (Hiroshima Univ.), Akira Tsuchiya (Kyoto Univ.), Pham Konkuha (Univ. of Electro-Comm.) =============================================== Technical Committee on Image Engineering (IE) Chair: Toshiaki Fujii (Nagoya Univ.) Vice Chair: Seishi Takamura (NTT), Takayuki Hamamoto (Tokyo Univ. of Science) Secretary: Akira Kubota (Chuo Univ.), Atsuro Ichigaya (NHK) Assistant: Hiroshi Sankoh (KDDI R&D Labs.), Shohei Matsuo (NTT) =============================================== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) Chair: Michiaki Muraoka (Kochi Univ.) Secretary: Naoki Iwata (Sony), Kotaro Shimamura (Hitachi), Makoto Sugihara (Kyushu Univ.) DATE: Mon, Oct 7, 2013 10:30 - 16:55 Tue, Oct 8, 2013 09:00 - 12:15 PLACE: TOPICS: ---------------------------------------- Mon, Oct 7 AM VLD(1) (10:30 - 11:45) Chair: Atsushi Kurokawa (Hirosaki Univ.) ---------------------------------------- (1)/VLD 10:30 - 10:55 A Memory Based Filed Programmable Device for Energy saving MCUs Tetsuya Matsumura (Nihon Univ.), Yoshifumi Kawamura (Renesas Electronics), Naoya Okada (Kanazawa Univ.), Kazutami Arimoto (Okayama Prefectual Univ.), Hiroshi Makino (OIT), Yoshio Matsuda (Kanazawa Univ.) (2)/VLD 10:55 - 11:20 Proposal of Double-clock and Dual-Edge-Triggered Flip-flops for Asynchronous Circuits Masashi Imai (Hirosaki Univ.), Tomohiro Yoneda (NII) (3)/VLD 11:20 - 11:45 Construction of an Automatic Design Flow for Dual Pipelined Self-Synchronous Circuit Atsushi Ito, Makoto Ikeda (Univ. of Tokyo) ----- Lunch ( 75 min. ) ----- ---------------------------------------- Mon, Oct 7 PM (13:00 - 14:00) Chair: Michiaki Muraoka (Kochi Univ.) ---------------------------------------- (4)/VLD 13:00 - 14:00 [Invited Talk] Technology Trends and Researches in Video Codec LSI Satoshi Goto (Waseda Univ.) ----- Break ( 20 min. ) ----- ---------------------------------------- Mon, Oct 7 PM (14:20 - 15:20) Chair: Makoto Ikeda (Univ. of Tokyo) ---------------------------------------- (5)/VLD 14:20 - 15:20 [Invited Talk] Standardization of HEVC/H.265 and a Real-time Encoder Hiroharu Sakate, Nobuaki Motoyama (Mitsubishi Electric) ----- Break ( 20 min. ) ----- ---------------------------------------- Mon, Oct 7 PM IE/ICD(1) (15:40 - 16:55) Chair: Atsuro Ichigaya (NHK) ---------------------------------------- (6)/IE 15:40 - 16:05 High Speed Block Motion Estimation (BME) Employing "Picture Frame shaped Search Window (PFSW)" for 8K Ultra High Definition Television (UHDTV) Kentaro Seki, Tadayoshi Enomoto (Chuo Univ.) (7)/ICD 16:05 - 16:30 A 2.4x-Real-Time VLSI Processor for 60-kWord Continuous Speech Recognition Guangji He, Yuki Miyamoto, Kumpei Matsuda, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ) (8)/ICD 16:30 - 16:55 Set Operating Processor (SOP) -- Application for Image recognition -- Katsumi Inoue (AOT), Duc-Hung Le, Masahiro Sowa, Cong-Kha Pham (UEC) ---------------------------------------- Tue, Oct 8 AM VLD(2) (09:00 - 10:15) Chair: Makoto Sugihara (Kyushu Univ.) ---------------------------------------- (9)/VLD 09:00 - 09:25 A High-Level Synthesis Algorithm with Post-Silicon Delay Tuning for RDR Architectures and its Experimental Evaluations Yuta Hagio, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) (10)/VLD 09:25 - 09:50 Scan-based attack on the LED block cipher using scan signatures Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) (11)/VLD 09:50 - 10:15 A Bi-Linear Interpolation Unit Using Selector Logics Masashi Shio, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) ----- Break ( 20 min. ) ----- ---------------------------------------- Tue, Oct 8 AM ICD/VLD(1) (10:35 - 12:15) Chair: Takeshi Yamamura (Fujitsu Labs.) ---------------------------------------- (12)/ICD 10:35 - 11:00 New Architecture for Multiple-Valued Fine-Grain Reconfigurable VLSI Based on Current-Mode Logic Xu Bai, Michitaka Kameyama (Tohoku Univ.) (13)/ICD 11:00 - 11:25 A Low Supply Voltage, Large "Read" Margin, Six-Transistor CMOS SRAM Employing Adaptively Lowering Word Line Voltage Nobuaki Kobayashi, Tadayoshi Enomoto (Chuo Univ.) (14)/VLD 11:25 - 11:50 A Delay-Locked Loop with Multi-Level Channel Length Decomposed Programming Delay Elements Yu Zhang, Mingyu Li, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu), Bo Yang (Design Algorithm Lab) (15)/VLD 11:50 - 12:15 A 9-bit, 20MS/s SAR ADC with A Design Strategy by Synthesizing Consideration of Layout-Dependent Effects Gong Chen, Mingyu Li, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu), Bo Yang (Design Algorithm Lab) # Information for speakers General Talk will have 20 minutes for presentation and 5 minutes for discussion. === Technical Committee on VLSI Design Technologies (VLD) === # FUTURE SCHEDULE: Fri, Nov 15, 2013 - Sat, Nov 16, 2013: Ho Chi Minh City (Vietnam) [Sat, Aug 10], Topics: The 4th IEICE International Conference on Integrated Circuits Design and Verification (ICDV2013) Wed, Nov 27, 2013 - Fri, Nov 29, 2013: [Tue, Sep 17], Topics: Design Gaia 2013 -New Field of VLSI Design- Tue, Jan 28, 2014 - Wed, Jan 29, 2014: Hiyoshi Campus, Keio University [Fri, Nov 15], Topics: FPGA Applications, etc # SECRETARY: Shigetoshi Nakatake (Univ. of Kitakyushu) E-mail:       k -u # ANNOUNCEMENT: # See also VLD's homepage: http://www.ieice.org/~vld/ === Technical Committee on Integrated Circuits and Devices (ICD) === # FUTURE SCHEDULE: Fri, Nov 15, 2013 - Sat, Nov 16, 2013: Ho Chi Minh City (Vietnam) [Sat, Aug 10], Topics: The 4th IEICE International Conference on Integrated Circuits Design and Verification (ICDV2013) Mon, Nov 18, 2013: Tokyo Institute of Technology , Topics: Analog RF Wed, Nov 27, 2013 - Fri, Nov 29, 2013: [Tue, Sep 17], Topics: Design Gaia 2013 -New Field of VLSI Design- Tue, Jan 28, 2014 - Wed, Jan 29, 2014: Kyoto Univ. Tokeidai Kinenkan [Fri, Nov 22] # SECRETARY: Osamu Watanabe (Toshiba Corp.) E-mail:o   7  be  ba === Technical Committee on Image Engineering (IE) === # FUTURE SCHEDULE: Mon, Nov 25, 2013 - Tue, Nov 26, 2013: Kurume National College of Technology [Wed, Sep 18] Thu, Dec 5, 2013 - Fri, Dec 6, 2013: 60th Anniversary Hall, Kyoto Institute of Technology [Fri, Oct 18], Topics: Image Coding, Streaming, etc. # SECRETARY: Atsuro Ichigaya (NHK) E-mail: ie- n 2013  === Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) === # FUTURE SCHEDULE: Wed, Nov 27, 2013 - Fri, Nov 29, 2013: [Tue, Sep 17], Topics: Design Gaia 2013 -New Field of VLSI Design- Tue, Jan 28, 2014 - Wed, Jan 29, 2014: Hiyoshi Campus, Keio University [Fri, Nov 15], Topics: FPGA Applications, etc # SECRETARY: Makoto Sugihara (Kyushu Univ.)  gi  slrckshu-u# ANNOUNCEMENT: # Please see the IPSJ-SLDM page below: http://www.sig-sldm.org/ Last modified: 2013-10-08 10:37:05 |
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