ken-system: Advance Program - 2013-10-IE-ICD-VLD-IPSJ-SLDM

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Technical Committee on VLSI Design Technologies (VLD)

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Chair		Makoto Ikeda (Univ. of Tokyo)
Vice Chair		Toshiyuki Shibuya (Fujitsu Labs.)
Secretary		Shigetoshi Nakatake (Univ. of Kitakyushu), Noriyuki Minegishi (Mitsubishi Electric)

Technical Committee on Integrated Circuits and Devices (ICD)

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Chair		Takeshi Yamamura (Fujitsu Labs.)
Vice Chair		Minoru Fujishima (Hiroshima Univ.)
Secretary		Toshimasa Matsuoka (Osaka Univ.), Osamu Watanabe (Toshiba)
Assistant		Shinichi Ouchi (AIST), Takeshi Yoshida (Hiroshima Univ.), Akira Tsuchiya (Kyoto Univ.), Pham Konkuha (Univ. of Electro-Comm.)

Technical Committee on Image Engineering (IE)

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Chair		Toshiaki Fujii (Nagoya Univ.)
Vice Chair		Seishi Takamura (NTT), Takayuki Hamamoto (Tokyo Univ. of Science)
Secretary		Akira Kubota (Chuo Univ.), Atsuro Ichigaya (NHK)
Assistant		Hiroshi Sankoh (KDDI R&D Labs.), Shohei Matsuo (NTT)

Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)

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Chair		Michiaki Muraoka (Kochi Univ.)
Secretary		Naoki Iwata (Sony), Kotaro Shimamura (Hitachi), Makoto Sugihara (Kyushu Univ.)

Conference Date	Mon, Oct 7, 2013 10:30 - 16:55 Tue, Oct 8, 2013 09:00 - 12:15
Topics
Conference Place

Mon, Oct 7 AM VLD(1) Chair: Atsushi Kurokawa (Hirosaki Univ.) 10:30 - 11:45
(1) VLD	10:30-10:55	A Memory Based Filed Programmable Device for Energy saving MCUs	Tetsuya Matsumura (Nihon Univ.), Yoshifumi Kawamura (Renesas Electronics), Naoya Okada (Kanazawa Univ.), Kazutami Arimoto (Okayama Prefectual Univ.), Hiroshi Makino (OIT), Yoshio Matsuda (Kanazawa Univ.)
(2) VLD	10:55-11:20	Proposal of Double-clock and Dual-Edge-Triggered Flip-flops for Asynchronous Circuits	Masashi Imai (Hirosaki Univ.), Tomohiro Yoneda (NII)
(3) VLD	11:20-11:45	Construction of an Automatic Design Flow for Dual Pipelined Self-Synchronous Circuit	Atsushi Ito, Makoto Ikeda (Univ. of Tokyo)
	11:45-13:00	Lunch ( 75 min. )
Mon, Oct 7 PM Chair: Michiaki Muraoka (Kochi Univ.) 13:00 - 14:00
(4) VLD	13:00-14:00	[Invited Talk] Technology Trends and Researches in Video Codec LSI	Satoshi Goto (Waseda Univ.)
	14:00-14:20	Break ( 20 min. )
Mon, Oct 7 PM Chair: Makoto Ikeda (Univ. of Tokyo) 14:20 - 15:20
(5) VLD	14:20-15:20	[Invited Talk] Standardization of HEVC/H.265 and a Real-time Encoder	Hiroharu Sakate, Nobuaki Motoyama (Mitsubishi Electric)
	15:20-15:40	Break ( 20 min. )
Mon, Oct 7 PM IE/ICD(1) Chair: Atsuro Ichigaya (NHK) 15:40 - 16:55
(6) IE	15:40-16:05	High Speed Block Motion Estimation (BME) Employing "Picture Frame shaped Search Window (PFSW)" for 8K Ultra High Definition Television (UHDTV)	Kentaro Seki, Tadayoshi Enomoto (Chuo Univ.)
(7) ICD	16:05-16:30	A 2.4x-Real-Time VLSI Processor for 60-kWord Continuous Speech Recognition	Guangji He, Yuki Miyamoto, Kumpei Matsuda, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ)
(8) ICD	16:30-16:55	Set Operating Processor (SOP) -- Application for Image recognition --	Katsumi Inoue (AOT), Duc-Hung Le, Masahiro Sowa, Cong-Kha Pham (UEC)
Tue, Oct 8 AM VLD(2) Chair: Makoto Sugihara (Kyushu Univ.) 09:00 - 10:15
(9) VLD	09:00-09:25	A High-Level Synthesis Algorithm with Post-Silicon Delay Tuning for RDR Architectures and its Experimental Evaluations	Yuta Hagio, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
(10) VLD	09:25-09:50	Scan-based attack on the LED block cipher using scan signatures	Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
(11) VLD	09:50-10:15	A Bi-Linear Interpolation Unit Using Selector Logics	Masashi Shio, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
	10:15-10:35	Break ( 20 min. )
Tue, Oct 8 AM ICD/VLD(1) Chair: Takeshi Yamamura (Fujitsu Labs.) 10:35 - 12:15
(12) ICD	10:35-11:00	New Architecture for Multiple-Valued Fine-Grain Reconfigurable VLSI Based on Current-Mode Logic	Xu Bai, Michitaka Kameyama (Tohoku Univ.)
(13) ICD	11:00-11:25	A Low Supply Voltage, Large "Read" Margin, Six-Transistor CMOS SRAM Employing Adaptively Lowering Word Line Voltage	Nobuaki Kobayashi, Tadayoshi Enomoto (Chuo Univ.)
(14) VLD	11:25-11:50	A Delay-Locked Loop with Multi-Level Channel Length Decomposed Programming Delay Elements	Yu Zhang, Mingyu Li, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu), Bo Yang (Design Algorithm Lab)
(15) VLD	11:50-12:15	A 9-bit, 20MS/s SAR ADC with A Design Strategy by Synthesizing Consideration of Layout-Dependent Effects	Gong Chen, Mingyu Li, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu), Bo Yang (Design Algorithm Lab)

Announcement for Speakers
General Talk	Each speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD	Technical Committee on VLSI Design Technologies (VLD) [Latest Schedule]
	Contact Address	Shigetoshi Nakatake (Univ. of Kitakyushu) E-: k-u
	Announcement	See also VLD's homepage: http://www.ieice.org/~vld/
ICD	Technical Committee on Integrated Circuits and Devices (ICD) [Latest Schedule]
	Contact Address	Osamu Watanabe (Toshiba Corp.) E-:o7beba
IE	Technical Committee on Image Engineering (IE) [Latest Schedule]
	Contact Address	Atsuro Ichigaya (NHK) E-: ie-n2013
IPSJ-SLDM	Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [Latest Schedule]
	Contact Address	Makoto Sugihara (Kyushu Univ.) Email gislrckshu-u
	Announcement	Please see the IPSJ-SLDM page below: http://www.sig-sldm.org/