Mon, Oct 7 AM VLD(1) Chair: Atsushi Kurokawa (Hirosaki Univ.) 10:30 - 11:45 |
(1) VLD |
10:30-10:55 |
A Memory Based Filed Programmable Device for Energy saving MCUs |
Tetsuya Matsumura (Nihon Univ.), Yoshifumi Kawamura (Renesas Electronics), Naoya Okada (Kanazawa Univ.), Kazutami Arimoto (Okayama Prefectual Univ.), Hiroshi Makino (OIT), Yoshio Matsuda (Kanazawa Univ.) |
(2) VLD |
10:55-11:20 |
Proposal of Double-clock and Dual-Edge-Triggered Flip-flops for Asynchronous Circuits |
Masashi Imai (Hirosaki Univ.), Tomohiro Yoneda (NII) |
(3) VLD |
11:20-11:45 |
Construction of an Automatic Design Flow for Dual Pipelined Self-Synchronous Circuit |
Atsushi Ito, Makoto Ikeda (Univ. of Tokyo) |
|
11:45-13:00 |
Lunch ( 75 min. ) |
Mon, Oct 7 PM Chair: Michiaki Muraoka (Kochi Univ.) 13:00 - 14:00 |
(4) VLD |
13:00-14:00 |
[Invited Talk]
Technology Trends and Researches in Video Codec LSI |
Satoshi Goto (Waseda Univ.) |
|
14:00-14:20 |
Break ( 20 min. ) |
Mon, Oct 7 PM Chair: Makoto Ikeda (Univ. of Tokyo) 14:20 - 15:20 |
(5) VLD |
14:20-15:20 |
[Invited Talk]
Standardization of HEVC/H.265 and a Real-time Encoder |
Hiroharu Sakate, Nobuaki Motoyama (Mitsubishi Electric) |
|
15:20-15:40 |
Break ( 20 min. ) |
Mon, Oct 7 PM IE/ICD(1) Chair: Atsuro Ichigaya (NHK) 15:40 - 16:55 |
(6) IE |
15:40-16:05 |
High Speed Block Motion Estimation (BME) Employing "Picture Frame shaped Search Window (PFSW)" for 8K Ultra High Definition Television (UHDTV) |
Kentaro Seki, Tadayoshi Enomoto (Chuo Univ.) |
(7) ICD |
16:05-16:30 |
A 2.4x-Real-Time VLSI Processor for 60-kWord Continuous Speech Recognition |
Guangji He, Yuki Miyamoto, Kumpei Matsuda, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ) |
(8) ICD |
16:30-16:55 |
Set Operating Processor (SOP)
-- Application for Image recognition -- |
Katsumi Inoue (AOT), Duc-Hung Le, Masahiro Sowa, Cong-Kha Pham (UEC) |
Tue, Oct 8 AM VLD(2) Chair: Makoto Sugihara (Kyushu Univ.) 09:00 - 10:15 |
(9) VLD |
09:00-09:25 |
A High-Level Synthesis Algorithm with Post-Silicon Delay Tuning for RDR Architectures and its Experimental Evaluations |
Yuta Hagio, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) |
(10) VLD |
09:25-09:50 |
Scan-based attack on the LED block cipher using scan signatures |
Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) |
(11) VLD |
09:50-10:15 |
A Bi-Linear Interpolation Unit Using Selector Logics |
Masashi Shio, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) |
|
10:15-10:35 |
Break ( 20 min. ) |
Tue, Oct 8 AM ICD/VLD(1) Chair: Takeshi Yamamura (Fujitsu Labs.) 10:35 - 12:15 |
(12) ICD |
10:35-11:00 |
New Architecture for Multiple-Valued Fine-Grain Reconfigurable VLSI Based on Current-Mode Logic |
Xu Bai, Michitaka Kameyama (Tohoku Univ.) |
(13) ICD |
11:00-11:25 |
A Low Supply Voltage, Large "Read" Margin, Six-Transistor CMOS SRAM Employing Adaptively Lowering Word Line Voltage |
Nobuaki Kobayashi, Tadayoshi Enomoto (Chuo Univ.) |
(14) VLD |
11:25-11:50 |
A Delay-Locked Loop with Multi-Level Channel Length Decomposed Programming Delay Elements |
Yu Zhang, Mingyu Li, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu), Bo Yang (Design Algorithm Lab) |
(15) VLD |
11:50-12:15 |
A 9-bit, 20MS/s SAR ADC with A Design Strategy by Synthesizing Consideration of Layout-Dependent Effects |
Gong Chen, Mingyu Li, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu), Bo Yang (Design Algorithm Lab) |