ken-system: Advance Program - 2010-07-ICD-ITE-IST

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Technical Committee on Integrated Circuits and Devices (ICD)
Chair: Kunio Uchiyama (Hitachi) Vice Chair: Masahiko Yoshimoto (Kobe Univ.), Toshihiko Hamasaki (TI)
Secretary: Yoshio Hirose (Fujitsu Labs.), Hiroaki Suzuki (Renesas)
Assistant: Toshimasa Matsuoka (Osaka Univ.), Ken Takeuchi (Univ. of Tokyo), Kenichi Okada (Tokyo Inst. of Tech.)

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Technical Group on Information Sensing Technologies (ITE-IST)
Chair: Jun Ohta (NAIST) Vice Chair: Isao Takayanagi (Aptina), Shigetoshi Sugawa (Tohoku Univ.)
Secretary: Masayuki Ikebe (Hokkaido Univ.)

DATE:
Thu, Jul 22, 2010 09:30 - 18:20
Fri, Jul 23, 2010 09:15 - 17:50

PLACE:
Josho Gakuen Osaka Center(http://www.josho.ac.jp/osakacenter/index.html. Prof. Hiroshi Makino. 06-6346-6367 (Hall))

TOPICS:
Analog, Mixed analog and digital, RF, and sensor interface circuitry

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Thu, Jul 22 AM (09:30 - 11:10)
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(1)/ICD 09:30 - 09:55
On-Chip Waveform Capture and Diagnosis of Power Delivery in SoC Integration
Takushi Hashida, Hiroshi Matsumoto, Makoto Nagata (Kobe Univ.)

(2)/ICD 09:55 - 10:20
Evaluation of algorithms for waveform acquisition in on-chip multi-channel monitoring
Yuuki Araga, Takushi Hashida, Makoto Nagata (Kobe Univ.)

(3)/ICD 10:20 - 10:45
In-situ Evaluation of Vth and AC Gain of 90 nm CMOS Differential Pair Transistors
Yoji Bando, Satoshi Takaya, Takashi Hasegawa (Kobe Univ.), Toru Ohkawa, Masaaki Souda, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami (MIRAI-Selete), Makoto Nagata (Kobe Univ.)

(4)/ICD 10:45 - 11:10
Buffer-Ring-Based All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Effect
Tetsuya Iizuka, Toru Nakura, Kunihiro Asada (Univ. of Tokyo)

----- Break ( 10 min. ) -----

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Thu, Jul 22 AM (11:20 - 13:00)
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(5)/ICD 11:20 - 12:10
[Invited Talk]
Digital Calibration and Correction Methods for CMOS-ADCs
Shiro Dosho (Panasonic Corp.)

(6)/ICD 12:10 - 13:00
[Invited Talk]
A 10b 50MS/s 820uW SAR ADC with on-chip digital calibration
Sanroku Tsukamoto (Fujitsu Labs.)

----- Lunch Break ( 60 min. ) -----

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Thu, Jul 22 PM (14:00 - 15:40)
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(7)/ICD 14:00 - 14:50
[Invited Talk]
Digitally-Assisted Analog Test Technology
-- Analog Circuit Test Technology in Nano-CMOS Era --
Haruo Kobayashi, Takahiro J. Yamaguchi (Gunma Univ.)

(8)/ICD 14:50 - 15:40
[Invited Talk]
Technical Trend of Multi-mode Multi-band RF Transceivers
Hisayasu Sato (Renesas Electronics)

----- Break ( 10 min. ) -----

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Thu, Jul 22 PM (15:50 - 18:20)
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(9)/ICD 15:50 - 16:40
[Invited Talk]
A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer with a Time-Windowed Time-to-Digital Converter
Tadashi Maeda, Takashi Tokairin (Renesas Electronics Corporation), Masaki Kitsunezuka (NEC Corp.), Mitsuji Okada (Renesas Electronics Corporation), Muneo Fukaishi (NEC Corp.)

----- Break ( 10 min. ) -----

(10) 16:50 - 18:20
Panel Discussion

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Fri, Jul 23 AM (09:15 - 10:55)
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(11)/ICD 09:15 - 09:40
Implementation and Evaluation of a CMOS Subthreshold Analog Amplifier using 0.5V Power Supply
Tomochika Harada (Yamagata Univ.)

(12)/ICD 09:40 - 10:05
OTA Design Using gm/ID Lookup Table Methodology
-- Design optimization featuring settling time analysis --
Toru Kashimura, Takayuki Konishi, Shoichi Masui (Tohoku Univ.)

(13)/ICD 10:05 - 10:30
Considerations of a Common-mode Feedback Circuit in the CMOS Inverter-based Differential Amplifier.
Masayuki Uno (Linear Cell Design)

(14)/ICD 10:30 - 10:55
The Design of a Highly Linearized Gm Amplifier by Adopting the Positive Feedback Compensation Scheme and its Application to High-Frequency Filters
Yusuke Shimoyama, Yasuhiro Sugimoto (Chuo Univ.)

----- Break ( 10 min. ) -----

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Fri, Jul 23 AM (11:05 - 12:20)
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(15)/ICD 11:05 - 11:30
On-chip background calibration of time-interleaved ADC
Takashi Oshima, Tomomi Takahashi (Hitachi)

(16)/ITE-IST 11:30 - 11:55
A/D converter for CMOS Image Sensor with a variable gain amplifier features
Tetsuya Iida, Tomoyuki Akahori (BT), Mohd Amrallah Bin Mustafa, Keita Yasutomi, Shoji Kawahito (Shizuoka Univ.)

(17)/ICD 11:55 - 12:20
Interleaved ramp wave generator for single slope ADC
Yukinobu Makihara, Shin Muon, Masayuki Ikebe, Junichi Motohisa, Eiichi Sano (Hokkaido Univ.)

----- Lunch Break ( 60 min. ) -----

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Fri, Jul 23 PM (13:20 - 15:00)
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(18)/ITE-IST 13:20 - 14:10
[Invited Talk]
An All-Digital and Scalable Time-Mode A/D Converter TAD
-- Challenge for Sensor Circuit Digitalization --
Takamoto Watanabe (DENSO)

(19)/ITE-IST 14:10 - 15:00
[Invited Talk]
TDC and SOI Radiation Image Sensor for Particle Physics
Yasuo Arai (KEK IPNS)

----- Break ( 10 min. ) -----

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Fri, Jul 23 PM (15:10 - 16:25)
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(20)/ITE-IST 15:10 - 15:35
Low noise sensor signal readout circuits with a response time acceleration technique
Mars Kamel, Shoji Kawahito (Shizuoka Univ.)

(21)/ITE-IST 15:35 - 16:00
Design and Development of Polarization-Analyzing Image Sensor using 65nm CMOS Process
Sanshiro Shishido, Toshihiko Noda, Kiyotaka Sasagawa, Takashi Tokuda, Jun Ohta (NAIST)

(22)/ICD 16:00 - 16:25
User Customizable Logic Paper with 2V Organic CMOS and Ink-Jet Printed Interconnects
Koichi Ishida, Naoki Masunaga, Ryo Takahashi, Tsuyoshi Sekitani (Univ. of Tokyo), Shigeki Shino (Mitsubishi Paper Mills Ltd.), Ute Zschieschang, Hagen Klauk (Max Planck Institute), Makoto Takamiya, Takao Someya, Takayasu Sakurai (Univ. of Tokyo)

----- Break ( 10 min. ) -----

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Fri, Jul 23 PM (16:35 - 17:50)
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(23)/ICD 16:35 - 17:00
Self-Dithered Digital Delta Sigma Modulators for Fractional-N Frequency Synthesizers
Zule Xu, Jun Gyu Lee, Shoichi Masui (Tohoku Univ.)

(24)/ICD 17:00 - 17:25
A Study of Simulation Methodologies to Simulate the Buck and Boost DC-DC Converters in High-Speed
Masahiro Suzuki (Chuo Univ.), Syoko Sugimoto (AdIn), Yasuhiro Sugimoto (Chuo Univ.)

(25)/ICD 17:25 - 17:50
Level Converter Circuit for Low Voltage Digital LSIs
Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ.)

# Information for speakers
General Talk will have 20 minutes for presentation and 5 minutes for discussion.
Invited Talk will have 40 minutes for presentation and 10 minutes for discussion.

# CONFERENCE SPONSORS:
- This conference is co-sponsored by IEEE SSCS Japan/Kansai Chapter

=== Technical Committee on Integrated Circuits and Devices (ICD) ===
# FUTURE SCHEDULE:

Mon, Aug 16, 2010 - Wed, Aug 18, 2010: Ho Chi Minh City University of Technology [Tue, Jun 15], Topics: Integrated Circuits and Devices in Vietnam 2010
Thu, Aug 26, 2010 - Fri, Aug 27, 2010: Sapporo Center for Gender Equality [Wed, Jun 9], Topics: Low voltage/low power techniques, novel devices, circuits, and applications
Tue, Oct 5, 2010 - Wed, Oct 6, 2010: Makuhari Messe, International Conference Hall [Wed, Jul 21], Topics: Frontier of processor, DSP, and image processing supporting Digital Harmony

# SECRETARY:
Toshimasa Matsuoka (Osaka University)
TEL 06-6879-7792,FAX 06-6879-7792
E-mail: