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Technical Committee on VLSI Design Technologies (VLD)

Chair		Nagisa Ishiura (Kwansei Gakuin Univ.)
Vice Chair		Kazutoshi Wakabayashi (NEC)
Secretary		Hiroyuki Ochi (Kyoto Univ.), Ichiro Kohno (Renesas)

Technical Committee on Silicon Device and Materials (SDM)

[schedule] [select]

Chair		Tanemasa Asano (Kyushu Univ.)
Vice Chair		Toshihiro Sugii (Fujitsu)
Secretary		Shigeru Kawanaka (Toshiba), Hisahiro Anzai (Sony)
Assistant		Syunichiro Ohmi (Tokyo Inst. of Tech.)

Conference Date	Tue, Oct 30, 2007 10:00 - 16:15 Wed, Oct 31, 2007 10:00 - 16:15
Topics	Process, Device, Circuit Simulation, etc.
Conference Place
Transportation Guide	http://www.jspmi.or.jp/

Tue, Oct 30 AM 10:00 - 11:40
(1)	10:00-10:25	Simulation on the electric conduction of semiconductor with arrayed dopant	Tomohide Terunuma, Takanobu Watanabe (Waseda Univ.), Takahiro Shinada (ASMeW), Yoshinari Kamakura, Kenji Taniguchi (Osaka Univ.), Iwao Ohdomari (Waseda Univ.)
(2)	10:25-10:50	Comparative Study on Drive Current of non-Si n-Channel MOSFETs based on Quantum-Corrected Monte Calro Simulation	Takashi Mori, Yuusuke Azuma, Hideaki Tsuchiya (Kobe Univ.)
(3)	10:50-11:15	Coarse-grain quantum transport simulation of ultra-small MOSFETs	Gennady Mil'nikov, Nobuya Mori, Yoshinari Kamakura (Osaka Univ.), Tatsuya Ezaki (Hiroshima Univ.)
(4)	11:15-11:40	Crystalline Orientation effects on device characteristics in ultra-small multi-gate devices	Hideki Minari, Daisuke Nishitani, Nobuya Mori (Osaka Univ.)
	11:40-13:00	Lunch ( 80 min. )
Tue, Oct 30 PM 13:00 - 14:35
(5)	13:00-13:45	[Invited Talk] Simulation technology for power devices	Ichiro Omura (Toshiba)
(6)	13:45-14:10	Electro-Thermal Compact Model for Reset Operation of Phase Change Memories	Atsushi Sakai, Kenichiro Sonoda, Masahiro Moniwa, Kiyoshi Ishikawa, Osamu Tsuchiya, Yasuo Inoue (Renesas Technology Corp.)
(7)	14:10-14:35	Study of Parasitic Resistance Behavior and Its Extraction Method on Deeply Scaled MOSFETs	Hideji Tsujii, Akira Hokazono, Makoto Fujiwara, Shigeru Kawanaka, Atsushi Azuma, Nobutoshi Aoki, Yoshiaki Toyoshima (Toshiba)
	14:35-15:00	Break ( 25 min. )
Tue, Oct 30 PM 15:00 - 16:15
(8)	15:00-15:25	Impact of Shear Strain and Quantum Confinement on <110> Channel nMOSFET with High-Stress CESL	Hiroyuki Takashino, Takeshi Okagaki, Tetsuya Uchida, Takashi Hayashi, Motoaki Tanizawa, Eiji Tsukuda, Katsumi Eikyu, Shoji Wakahara, Kiyoshi Ishikawa, Osamu Tsuchiya, Yasuo Inoue (Renesas Technology Corp.)
(9)	15:25-15:50	Analysis of strain-dependent hole transport characteristics in bulk Ge-pMOSFETs	Hiroshi Takeda (NEC), Takeo Ikezawa, Michihito Kawada (NIS), Masami Hane (NEC)
(10)	15:50-16:15	Validation of the Effect of Full Stress Tensor in HoleTransport in Strained 65nm-node pMOSFETs	Eiji Tsukuda (Renesas), Yoshinari Kamakura (Osaka Univ.), Hiroyuki Takashino, Takeshi Okagaki, Tetsuya Uchida, Takashi Hayashi, Motoaki Tanizawa, Katsumi Eikyu, Shoji Wakahara, Kiyoshi Ishikawa, Osamu Tsuchiya, Yasuo Inoue (Renesas), Kenji Taniguchi (Osaka Univ.)
Wed, Oct 31 AM 10:00 - 11:40
(11)	10:00-10:25	An analysis of retention time of a DORGA with a constant irradiation period	Daisaku Seto, Minoru Watanabe (Shizuoka Univ.)
(12)	10:25-10:50	Fast dynamic optical reconfigurations of multi-context ORGAs	Mao Nakajima, Minoru Watanabe (Shizuoka Univ.)
(13)	10:50-11:15	Fast optical configurations using context superimposition	Naoki Yamaguchi, Minoru Watanabe (Shizuoka Univ.)
(14)	11:15-11:40	Study of litho weak points detecting method using TCC's eigen vector	Satoshi Yoshikawa (FUJITSU VLSI), Hiroki Futatuya, Tatsuo Chijimatsu, Satoru Asai (FUJITSU)
	11:40-13:00	Lunch Break ( 80 min. )
Wed, Oct 31 PM 13:00 - 14:40
(15)	13:00-13:50	[Invited Talk] TBD	Masanori Hashimoto (Osaka Univ.)
(16)	13:50-14:15	Analysis of Inverter and SRAM circuits characteristics fluctuation	Ryo Tanabe, Yoshio Ashizawa, Hideki Oka (Fujitsu Labs.)
(17)	14:15-14:40	The Analysis of MOSFET Characteristic Fluctuation Caused by Layout Variation	Kunio Anzai, Hitoshi Tsuno, Masao Matsumura, Satoe Minami, Yohei Hiura, Akira Takeo, Fu Wingsze, Yuzo Fukuzaki, Michihiro Kanno, Naoki Nagashima, Hisahiro Ansai (Sony)
	14:40-15:00	Break ( 20 min. )
Wed, Oct 31 PM 15:00 - 16:15
(18)	15:00-15:25	Scaled CMOS Modeling on Analog Small Signal parameters	Takeshi Kida, Shin-ichi Ohkawa, Hiroo Masuda (Renesas)
(19)	15:25-15:50	Modeling of Floating-Body Effect in SOI-MOSFET with Complete Surface-Potential Description	Takahiro Murakami, Makoto Ando, Norio Sadachika (Hiroshima Univ.), Takaki Yoshida (NIS), Mitiko Miura-Mattausch (Hiroshima Univ.)
(20)	15:50-16:15	Technical Trends of Mismatch Modeling on Analog CMOS Circuit	Hiroo Masuda, Takeshi Kida, Shin-ichi Ohkawa (Renesas)

Contact Address and Latest Schedule Information
VLD	Technical Committee on VLSI Design Technologies (VLD) [Latest Schedule]
	Contact Address	Hiroyuki OCHI (Kyoto Univ.) E-:oeek-u Tel.075-753-4803
	Announcement	See also VLD's homepage: http://www.ieice.org/~vld/
SDM	Technical Committee on Silicon Device and Materials (SDM) [Latest Schedule]
	Contact Address	Yasushiro Nishioka (Nihon University, College of Science and Technology) TEL047-469-6482,FAX047-467-9504 E-:etn-u,acmsk