Tue, Jan 19 AM 10:40 - 12:20 |
(1) RECONF |
10:40-11:05 |
Circuit Design of Reconfigurable Logic and Comparison of the Methods |
Junki Kato, Shigeyoshi Watanabe, Hiroshi Ninomiya, Manabu Kobayashi, Yasuyuki Miura (SIT) |
(2) RECONF |
11:05-11:30 |
FPGA routing structure based on H-Tree topology |
Yuki ishii, Masato Ikebe, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
(3) RECONF |
11:30-11:55 |
Pipelining in Coarse Grained Reconfigurable Accelerator CMA |
Naoki Ando, Koichiro Masuyama, Yu Fujita, Hideharu Amano (Keio Univ.) |
(4) RECONF |
11:55-12:20 |
A Low-Latency Batch Processing for Stream Data Using FPGA NIC |
Kohei Nakamura, Ami Hayashi, Hiroki Matsutani (Keio Univ.) |
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12:20-13:30 |
Lunch Break ( 70 min. ) |
Tue, Jan 19 PM 13:30 - 14:45 |
(5) CPSY |
13:30-13:55 |
Performance Evaluations on Reduction and Transformation of Spark Using GPU |
Yasuhiro Ohno, Shin Morishima, Hiroki Matsutani (Keio Univ.) |
(6) CPSY |
13:55-14:20 |
GPGPU Parallelization of a cerebral cortex model BESOM |
Hidemoto Nakada, Tatsuhiko Inoue, Yuji Ichisugi (AIST) |
(7) CPSY |
14:20-14:45 |
GPGPU Implementation of the MSD Method for Outlier Detection and Its Experimental Evaluation |
Shotaro Asano, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.) |
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14:45-15:00 |
Break ( 15 min. ) |
Tue, Jan 19 PM 15:00 - 16:40 |
(8) |
15:00-15:25 |
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(9) |
15:25-15:50 |
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(10) |
15:50-16:15 |
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(11) |
16:15-16:40 |
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16:40-16:55 |
Break ( 15 min. ) |
Tue, Jan 19 PM 16:55 - 18:10 |
(12) CPSY |
16:55-17:20 |
Cost Estimation Method based on CPU Architecture for Relational Database Query Optimization |
Tsuyoshi Tanaka (Tokyo Metropolitan Univ./Hitachi), Hiroshi Ishikawa (Tokyo Metropolitan Univ.) |
(13) CPSY |
17:20-17:45 |
Performance Improvement on In-Kernel NOSQL Cache for Range Queries |
Korechika Tamura, Hiroki Matsutani (Keio Univ.) |
(14) CPSY |
17:45-18:10 |
FPGA-based Parallel Processing of Sliding-Window Aggregate Queries on Data Streams |
Yoshimitsu Ogawa, Yasin Oge, Masato Yoshimi, Celimuge Wu, Tsutomu Yoshinaga (UEC) |
Wed, Jan 20 AM 09:00 - 10:15 |
(15) VLD |
09:00-09:25 |
A Chip Evaluation of the Heat Generation in 3D stacked LSI |
Tatsuya Wada, Kimiyosi Usami (Shibaura IT) |
(16) VLD |
09:25-09:50 |
Implementation and evaluation of Dynamic Multi-Vth methodology in Silicon-on-Thin-BOX |
Shohei Io, Hanano Suzuki, Shohei Nakamura, Kimiyoshi Usami (Shibaura IT) |
(17) VLD |
09:50-10:15 |
Control Signal Extraction for Backward Sequential Clock Gating |
Tomoya Goto, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) |
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10:15-10:30 |
Break ( 15 min. ) |
Wed, Jan 20 AM 10:30 - 11:45 |
(18) |
10:30-10:55 |
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(19) |
10:55-11:20 |
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(20) |
11:20-11:45 |
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11:45-12:00 |
Break ( 15 min. ) |
Wed, Jan 20 PM 12:00 - 13:00 |
(21) CPSY |
12:00-13:00 |
[Fellow Memorial Lecture]
Failure May teach Success
-- In Computer Architecture Research based on Real hardware -- |
Hideharu Aamano (Keio Univ.) |
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13:00-14:15 |
Break ( 75 min. ) |
Wed, Jan 20 PM 14:15 - 15:30 |
(22) RECONF |
14:15-14:40 |
Design of Stencil Computation based on Building-Cube Method on an FPGA Accelerator with High Level Synthesis |
Rie Soejima, Koji Okina, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) |
(23) RECONF |
14:40-15:05 |
FPGA-based Tsunami Simulator developed by using stream-computing hardware compiler |
Kohei Nagasu, Kentaro Sano (Tohoku Univ.), Fumiya Kono, Naohito Nakasato (The Univ. of Aizu) |
(24) RECONF |
15:05-15:30 |
A Parallel Algorithm for Realizing the MacCormack Scheme in Computational Fluid Dynamics and its FPGA Implementation |
Yusuke Haga, Shinobu Nagayama, Shin'ichi Wakabayashi, Masato Inagi (Hiroshima City Univ.) |
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15:30-15:45 |
Break ( 15 min. ) |
Wed, Jan 20 PM 15:45 - 17:25 |
(25) CPSY |
15:45-16:10 |
Topological Analysis of Low-Powered 3D-TESH Network |
Faiz Al Faisal (JAIST), Hafizur Rahman (IIUM), Yasushi Inoguchi (JAIST) |
(26) CPSY |
16:10-16:35 |
An Efficient NoC with Decentralized Routers |
Ryota Yasudo, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano, Tadao Nakamura (Keio Univ.) |
(27) CPSY |
16:35-17:00 |
A performance evaluation of PEACH3 |
Takahiro Kaneda, Chiharu Tsuruta (Keio Univ), Toshihiro Hanawa (UTokyo), Hideharu Amano (Keio Univ) |
(28) CPSY |
17:00-17:25 |
Latency Reduction on Inter-Component Communication across Racks using FSO |
Hiroaki Hara, Tomoya Ozaki (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano, Hiroki Matsutani (Keio Univ.) |
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Banquet |
Thu, Jan 21 AM 09:00 - 10:15 |
(29) RECONF |
09:00-09:25 |
Performance Improvement on Music Fingerprint Searching from Large-Scale Database by Using Probabilistic Bias |
Masahiro Fukuda, Yasushi Inoguchi (JAIST) |
(30) RECONF |
09:25-09:50 |
Discussion on FPGA implementation of real-time human detection using FIND features |
Yoshiki Hayashida, Masahito Oishi, Ryo Fujita, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) |
(31) RECONF |
09:50-10:15 |
FPGA Implementation of a Peak Detection System using AMPD Algorithm |
Fumihiko Iwasaki, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ) |
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10:15-10:30 |
Break ( 15 min. ) |
Thu, Jan 21 AM 10:30 - 11:45 |
(32) CPSY |
10:30-10:55 |
Power Optimization of a Reconfigurable Accelerator by Middle-grained Body Bias Control |
Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Hideharu Amano (Keio Univ.) |
(33) CPSY |
10:55-11:20 |
Power Reduction of TLB using Body Bias Control on SOTB |
Daiki Kawase, Hayate Okuhara, Hideharu Amano (Keio Univ.) |
(34) CPSY |
11:20-11:45 |
An Architectural Optimization for Software Defined SSD using Full System Simulator |
Shun Gokita, Satoshi Kazama, Seiki Shibata, Shinya Kuwamura, Eiji Yoshida, Junji Ogawa (FLL) |
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11:45-13:00 |
Lunch Break ( 75 min. ) |
Thu, Jan 21 PM 13:00 - 14:40 |
(35) VLD |
13:00-13:25 |
Mainframe Assembly to C translation in Legacy Migration |
Daisuke Fujiwara, Nagisa Ishiura, Ryo Sakai (Kwansei Gakuin Univ.), Ryo Aoki, Takashi Ogawara (SYSTEM'S) |
(36) VLD |
13:25-13:50 |
A floorplan-driven high-level synthesis algorithm resilient to dynamic delay variations |
Koki Igawa, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) |
(37) VLD |
13:50-14:15 |
Binary Synthesis Implementing External Interrupt Handler as Independent Module |
Naoya Ito, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) |
(38) VLD |
14:15-14:40 |
Write-Reduction using Encoding data on MLC for Non-Volatile Memories |
Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) |
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14:40-14:55 |
Break ( 15 min. ) |
Thu, Jan 21 PM 14:55 - 16:10 |
(39) RECONF |
14:55-15:20 |
A Realization of Deep Convolutional Neural Network using the Nested RNS on an FPGA including the Constant Division |
Hiroki Nakahara (Ehime Univ.), Tsutomu Sasao (Meiji Univ.), Hisashi Iwamoto (REVSONIC Corp.) |
(40) RECONF |
15:20-15:45 |
Implementation of TRAX Solver with Mate Structure |
Yasuhiro Takashima, Takaaki Yahata, Saki Yamaguchi, Komei Nomura (Univ. of Kitakyushu) |
(41) RECONF |
15:45-16:10 |
Search of Evaluation Function with Genetic Algorithm and UML Model-based Development for TRAX Player |
Ryo Tamaki, Naohiko Shimizu (Tokai Univ.) |