Mon, Nov 26 AM
10:30 - 11:45 |
(1)
VLD |
10:30-10:55 |
A Resource Sharing Method for Reconfigurable Systems with Java Virtual Machine
-- Programming in Instantiation -- |
Hitoki Ito, Kiyofumi Tanaka (JAIST) |
(2)
VLD |
10:55-11:20 |
Scalar replacement with exact analysis of array accesses |
Hiroaki Takehana, Kenshu Seto (Tokyo City Univ.) |
(3)
VLD |
11:20-11:45 |
A Temperature-Aware High-Level Synthesis Algorithm for Regular-Distributed-Register Architectures based on Accurate Energy Consumption Estimation |
Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) |
Mon, Nov 26 AM
10:30 - 11:45 |
(4)
VLD |
10:30-10:55 |
Automated Identification of Performance Bottleneck on Embedded Systems for Architecture Exploration |
Yuki Ando (Nagoya Univ.), Seiya Shibata (NEC), Shinya Honda (Nagoya Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroaki Takada (Nagoya Univ.) |
(5)
VLD |
10:55-11:20 |
An Efficient ZDD Construction Method Using Recursive Specifications |
Hiroaki Iwashita, Jun Kawahara (JST), Shin-ichi Minato (Hokkaido Univ.) |
(6)
VLD |
11:20-11:45 |
Partially-Programmable Circuits with CAMs |
Atsushi Matsuo, Shigeru Yamashita (Ritsumeikan Univ.), Hiroaki Yoshida (Fujitsu Laboratories of Amerika) |
Mon, Nov 26 PM
13:00 - 13:50 |
(7)
VLD |
13:00-13:50 |
[Invited Talk]
High Field Reliability Using Built-In Self Test |
Seiji Kajihara (Kyutech) |
Mon, Nov 26 PM Processor Architecture
14:30 - 15:20 |
(8)
CPSY |
14:30-14:55 |
Proposal of Speculative Memory Access Mechanism Based on Snoop Cache |
Yuji Sekiguchi, Hiroyoshi Jutori, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) |
(9)
CPSY |
14:55-15:20 |
A Study of Path Prediction Mechanism for Improving Accuracy by using Detailed History Information |
Hiroyoshi Jutori, Takanobu Baba, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota (Utsunomiya Univ.) |
Mon, Nov 26 PM
14:30 - 15:20 |
(10)
VLD |
14:30-15:20 |
[Invited Talk]
Development about LUMIX G Series, Digital Single-Lens Mirrorless Camera |
Shinobu Husa (Panasonic) |
Mon, Nov 26 PM Invited Talk
16:00 - 16:50 |
(11)
CPSY |
16:00-16:50 |
[Invited Talk]
Way Selection Cache for Low Power Computing |
Koji Inoue (Kyushu Univ.) |
Mon, Nov 26 PM
16:00 - 17:15 |
(12)
VLD |
16:00-16:25 |
Secure Scan Architecture Using State Dependent Scan Flip Flop with Key-Based Configuration against Scan-Based Attack |
Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) |
(13)
VLD |
16:25-16:50 |
Scan-based Attack against Camellia Cryptosystems |
Hirokazu Kodera, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) |
(14)
VLD |
16:50-17:15 |
A Delay Tuning Method of Programmable Delay Element with Two Delay Values for Yield Improvement |
Hayato Mashiko, Yukihide Kohira (UoA) |
Mon, Nov 26 PM
16:00 - 17:15 |
(15)
VLD |
16:00-16:25 |
Impact of Body-Biasing Technique on RTN-induced Delay Fluctuation |
Takashi Matsumoto (Kyoto Univ.), Kazutoshi Kobayashi (Kyoto Inst. Tech.), Hidetoshi Onodera (Kyoto Univ.) |
(16)
VLD |
16:25-16:50 |
A Low-Power and Area-Efficient Radiation-Hard Redundant Flip-Flop
-- DICE ACFF -- |
Kanto Kubota, Masaki Masuda, Kazutoshi Kobayashi (KIT) |
(17)
VLD |
16:50-17:15 |
Variations and BTI-induced Aging Degradation on Commercial FPGAs |
Shouhei Ishii, Kazutoshi Kobayashi (KIT) |
Tue, Nov 27 AM Network-on-a-Chip
09:00 - 10:15 |
(18)
CPSY |
09:00-09:25 |
A Routing Strategy for 3-D NoCs Incorporating Bus and Network |
Takahiro Kagami, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) |
(19)
CPSY |
09:25-09:50 |
Rethinking virtual channel usage in network-on-chip |
Ryosuke Sasakawa, Naoki Fujieda, Shinya Takamaeda-Yamazaki, Kenji Kise (Tokyo Tech) |
(20)
CPSY |
09:50-10:15 |
Network Performance of Multifunction On-chip Router Architectures |
Shinya Takamaeda-Yamazaki, Naoki Fujieda, Kenji Kise (Tokyo Inst. of Tech.) |
Tue, Nov 27 AM
09:00 - 10:00 |
(21)
CPM |
09:00-09:30 |
[Invited Talk]
High-Speed Interconnect Technologies |
Yutaka Uematsu, Go Shinkai, Satoshi Muraoka, Masayoshi Yagyu, Hideki Osaka (Hitachi) |
(22)
CPM |
09:30-10:00 |
[Invited Talk]
Passive Intermodulation Observed in linearly designed circuits |
Nobuhiro Kuga, Daijiro Ishibashi (Yokohama National Univ.) |
Tue, Nov 27 AM
09:00 - 10:15 |
(23)
VLD |
09:00-09:25 |
A Method to Parallelize Simulated Annealing Algorithm by Generating Look-ahead Neighbor Solutions |
Yusuke Ota, Kazuhito Ito (Saitama Univ.) |
(24)
VLD |
09:25-09:50 |
An Acceleration Method by GPGPU for Analytical Placement using Quasi-Newton Method |
Yukihide Kohira (UoA), Yasuhiro Takashima (Univ. of Kitakyushu) |
(25)
VLD |
09:50-10:15 |
An ILP Formulation of Placement and Routing for PLDs |
Hiroki Nishiyama, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ) |
Tue, Nov 27 AM
10:30 - 11:20 |
(26)
CPSY |
10:30-10:55 |
A study on Hardware Trojan embedded Manchurian and its detection approach for triple DES processing |
Youhei Mochizuki, Takeshi Kumaki (Ritsumeikan Univ), Masaya Yoshikawa (Meijo Univ), Takeshi Fujino (Ritsumeikan Univ) |
(27)
CPSY |
10:55-11:20 |
An FPGA Implementation of Reconfigurable Real-Time Vision Architecture |
Jorge Hiraiwa, Hideharu Amano (Keio Univ.) |
Tue, Nov 27 AM
10:15 - 11:45 |
(28)
CPM |
10:15-10:45 |
[Invited Talk]
Expectations to 2.5D/3D Package and Challenges on Package Design |
Hiroyuki Mori, Kazushige Toriyama, Yasumitsu Orii (IBM Japan) |
(29)
CPM |
10:45-11:15 |
[Invited Talk]
Overview of 3D Integration Technology and Challenges for Volume Production |
Kangwook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi (Tohoku Univ.) |
(30)
CPM |
11:15-11:45 |
[Invited Talk]
Novel Packaging Design by Appling Metamaterial Structures |
Takashi Harada, Hiroshi Toyao, Yoshiaki Kasahara (NEC Corp.) |
Tue, Nov 27 AM
10:30 - 11:45 |
(31)
VLD |
10:30-10:55 |
A speculative execution method for indefinite loops in high level synthesis |
Tatsuma Araki, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ) |
(32)
VLD |
10:55-11:20 |
A Behavioral Synthesis Method for Asynchronous Pipelined Circuits with Bundled-data Implementation |
Naohiro Hamada, Hiroshi Saito (The Univ. of Aizu) |
(33)
VLD |
11:20-11:45 |
Controller Synthesis for Clock Improvement in Behavioral Synthesis |
Ryoya Sobue (Ritsumeikan Univ.), Yuko Hara-Azumi (NAIST), Takuji Hieda, Ittetsu Taniguchi, Hiroyuki Tomiyama (Ritsumeikan Univ.) |
Tue, Nov 27 PM
13:00 - 13:50 |
(34)
RECONF |
13:00-13:50 |
[Invited Talk]
Application Examples of FPGA
-- Parallel Computers and Network -- |
Yuetsu Kodama (Univ. of Tsukuba) |
Tue, Nov 27 PM
13:50 - 14:40 |
(35)
RECONF |
13:50-14:15 |
Low Power Reconfiguarable Accelerator Design with Silicon on Thin Buried Oxide |
Hongliang Su, Weihan Wang, Hideharu Amano (Keio Univ.) |
(36)
RECONF |
14:15-14:40 |
A study on reconfigurable direct conversion JAVA accelerator for embedded systems |
Seiya Takada, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ) |
Tue, Nov 27 PM
13:00 - 14:40 |
(37)
VLD |
13:00-13:25 |
Accurate I/O Buffer Impedance Self-adjustment using Threshold Voltage and Temperature Sensors |
Zhi Li, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato (Kyoto Univ.) |
(38)
VLD |
13:25-13:50 |
Analytical model of energy dissipation for comparing adder architectures |
Nao Konishi, Kimiyoshi Usami (Shibaura I.T.) |
(39)
VLD |
13:50-14:15 |
Energy-efficient High-level Synthesis Considering Clock Design for HDR Architectures |
Hiroyuki Akasaka, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) |
(40)
VLD |
14:15-14:40 |
SAAV : Energy-efficient High-level Synthesis Algorithm targeting Adaptive Voltage Huddle-based Distributed Register Architecture with Dynamic Multiple Supply Voltages |
Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Institute of Technology Univ./Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) |
Tue, Nov 27 PM
13:00 - 14:40 |
(41)
DC |
13:00-13:25 |
Effective Orderings of Instances and Variable Assignments in SAT-based ATPG with Solution Reuse |
Kenji Ueda, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) |
(42)
DC |
13:25-13:50 |
A Heuristic Algorithm for Operational Unit Binding in Transient Fault Tolerant Datapath Synthesis |
Tatsuya Nakaso, Ryoko Ohkubo, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) |
(43)
VLD |
13:50-14:15 |
Dynamic Timing-Test Scheduling for Post-Silicon Skew Tuning |
Mineo Kaneko (JAIST) |
(44)
VLD |
14:15-14:40 |
A novel efficient data structure representing shared DAG patterns |
Yusuke Matsunaga (Kyushu Univ.) |
Tue, Nov 27 PM
15:00 - 16:30 |
| (45) |
15:00-16:30 |
|
Tue, Nov 27 PM Keynote Speach
17:00 - 18:00 |
| (46) |
17:00-18:00 |
[Keynote Address]
Dynamically Reconfigurable Processor (DRP) Technology: Current Status and Future Prospects |
Masato Motomura (Hokkaido Univ.), Koichiro Furuta, Toru Awashima, Yasunari Shida (Renesas Electronics) |
Wed, Nov 28 AM
09:00 - 10:15 |
(47)
RECONF |
09:00-09:25 |
A Basic Study of FPGA Routing Architecture Based on Scale Free Network |
Satoshi Hayama, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
(48)
RECONF |
09:25-09:50 |
0.18um CMOS process dynamic optically reconfigurable gate array VLSI |
Takayuki Kubota, Minoru Watanabe (Shizuoka Univ.) |
(49)
RECONF |
09:50-10:15 |
A 9-context optically reconfigurable gate array using a polymer-dispersed liquid crystal holographic memory |
Retsu Moriwaki, Minoru Watanabe (Shizuoka Univ.), Akifumi Ogiwara (Kobe City College of Tech.) |
Wed, Nov 28 AM
09:25 - 10:15 |
(50)
ICD |
09:25-09:50 |
A Single Chip Image Processor for Various In-car Display Equipments |
Yoshihiro Ogawa, Yoshiyuki Kato, Takashi Shinohara, Takeo Fujita, Noriyuki Minegishi (MITSUBISHI) |
(51)
ICD |
09:50-10:15 |
Development of SoC Fast Electric Power Estimation System FPA2 |
Takayuki Sasaki (FUJITSU LAB.) |
Wed, Nov 28 AM
09:00 - 10:15 |
(52)
VLD |
09:00-09:25 |
On Handling Cell Placement with Adjacent Common Centroid Constraints for Analog IC Layout Design |
Kunihiro Fujiyoshi, Keitaro Ue (TUAT) |
(53)
VLD |
09:25-09:50 |
Routability-oriented Common-Centroid Capacitor Array Generation |
Jing Li, Bo Yang (Design Algorithm Lab.), Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu) |
(54)
VLD |
09:50-10:15 |
Performance evaluation of Via Programmable Logic VPEX using P&R tool |
Taku Otani, Ryohei Hori, Taisuke Ueoka (Ritsumeikan Univ), Masaya Yoshikawa (Meijo Univ), Takeshi Fujino (Ritsumeikan Univ) |
Wed, Nov 28 AM
10:30 - 11:45 |
(55)
RECONF |
10:30-10:55 |
A Hardware Algorithm Using Dynamically Partially Reconfigurable FPGAs for Solving the Maximum Clique Problem of Large Graphs |
Chikako Miura, Shinobu Nagayama, Shin'ichi Wakabayashi, Masato Inagi (Hiroshima City Univ.) |
(56)
RECONF |
10:55-11:20 |
A Winning Board Detector Using an Index Generation Unit |
Kousiro Shiihara, Yuki Idokawa, Hiroki Nakahara (Kaoghima Univ.) |
(57)
RECONF |
11:20-11:45 |
An Implementation of a Tiny Spectrometer for a Radio Telescope on an Extensible Processing Platform |
Hiroki Nakahara, Hiroyuki Nakanishi (Kagosima Univ.), Tsutomu Sasao (KIT) |
Wed, Nov 28 AM
10:30 - 11:45 |
(58)
CPM |
10:30-10:55 |
Signal Evaluation Circuit for BD Multi-layer Recording |
Yusuke Nakamura, Hiroyuki Minemura, Takahiro Kurokawa, Taku Hoshizawa (Hitachi) |
(59)
ICD |
10:55-11:20 |
AES Cryptographic Circuit utilizing Dual-Rail RSL Memory Technique |
Yuki Hashimoto, Mitsuru Shiozaki, Takaya Kubota, Takeshi Fujino (Ritsumeikan Univ.) |
(60)
ICD |
11:20-11:45 |
Chip Design and Performance evaluation of Via Programmable Analog Circuit |
Keisuke Ueda, Ryo Nakazawa, Ryohei Hori, Mitsuru Shiozaki, Tomohiro Fujita, Takeshi Fujino (Ritsumeikan Univ.) |
Wed, Nov 28 AM
10:30 - 11:45 |
(61)
VLD |
10:30-10:55 |
A LSI-Package-Board co-evaluation of Power noise in the Digital LSI |
Kumpei Yoshikawa, Yuta Sasaki (Kobe Univ.), Kouji Ichikawa (DENSO), Yoshiyuki Saito (Panasonic), Makoto Nagata (Kobe Univ.) |
(62)
VLD |
10:55-11:20 |
Rational Function Approximation Using Vector Fitting and Equivalent Circuit Synthesis of Transmission Line Characteristics |
Daisuke Honda, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.) |
(63)
VLD |
11:20-11:45 |
High Sensitive Detection of Low S/N ratio Signal by Bistable Potential Circuit |
Hisaaki Kanai, Wen Li, Kengo Imagawa, Masami Makuuchi, Yutaka Uematsu, Hideki Osaka (Hitachi, Ltd.) |
Wed, Nov 28 PM
13:00 - 14:15 |
(64)
RECONF |
13:00-13:25 |
A Case Study of Short-term Development of Cooperation with FPGA-based System by Introducing Distributed-object ORB Engine |
Takeshi Ohkawa, Soshi Takano, Daichi Uetake, Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba (Utsunomiya Univ.) |
(65)
RECONF |
13:25-13:50 |
Performance Evaluation of RC-OS for Multiple FPGA Clusters |
Akira Kojima, Tetsuo Hironaka (Hiroshima City Univ.) |
(66)
RECONF |
13:50-14:15 |
The Attempt to Model-Based Hardware Development Using SysML |
Ryota Yamazaki (Tokai Univ), Naohiko Shimizu (Tokai Univ/IP ARCH Inc.) |
Wed, Nov 28 PM
13:25 - 14:15 |
(67)
VLD |
13:25-13:50 |
A 3D FPGA-Array HPC System "Vocalise" and its Performance Evaluation |
Yusuke Atsumari, Jiang Li, Hiromasa Kubo, Hakaru Tamukoh, Masatoshi Sekine (TUAT) |
(68)
VLD |
13:50-14:15 |
Performance evaluation of a TCP/IP Hardware Stack Directly Connectable to WEB Application Circuit |
Kotoko Fujita, Hakaru Tamukoh, Masatoshi Sekine (TUAT) |
Wed, Nov 28 PM
13:00 - 14:15 |
(69)
VLD |
13:00-13:25 |
The Fast Transient Analysis of The Power Distribution Network Modeled by Unstructured Meshes by Using Locally Implicit Latency Insertion Method (LIM) |
Shingo Okada, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.) |
(70)
VLD |
13:25-13:50 |
Explicit and Unconditionally Stable Finite Difference Scheme for the Fast Transient Analysis of the Power Distribution Network |
Norio Nishizaki, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.) |
(71)
VLD |
13:50-14:15 |
Control of Fine-Grain Power Gating by Detecting of the Virtual Ground Voltage |
Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.) |
Wed, Nov 28 PM
14:30 - 15:20 |
(72)
RECONF |
14:30-14:55 |
An observational study on fault-avoidance methods using dynamic partial reconfiguration |
Hiroaki Konoura (Osaka Univ.), Takashi Imagawa (Kyoto Univ.), Yukio Mitsuyama (Kochi Univ. of Tech.), Masanori Hashimoto, Takao Onoye (Osaka Univ.) |
(73)
RECONF |
14:55-15:20 |
Implementation of an Image Recognition System with Hierarchical Feature Learning Function |
Baku Ogasawara, Satoru Yokota, Hakaru Tamukoh, Masatoshi Sekine (TUAT) |
Wed, Nov 28 PM
14:30 - 15:20 |
(74)
VLD |
14:30-14:55 |
Energy Measurement and Analysis of ProcessingElement for Ultra Low Voltage |
Sachio Anzai, Masaru Kudo, Yuya Ota, Kazuki Ota, Kimiyoshi Usami (Sibaura Inst. Tech.) |
(75)
VLD |
14:55-15:20 |
Neutron Induced Single Event Multiple Transients With Voltage Scaling and Body Biasing |
Ryo Harada (Osaka Univ.), Yukio Mitsuyama (Kochi Univ. of Tech.), Masanori Hashimoto, Takao Onoye (Osaka Univ.) |
Wed, Nov 28 PM
14:30 - 15:45 |
(76)
VLD |
14:30-14:55 |
Design of temperature and voltage monitoring circuit structure for field test |
Wataru Tsumori, Yousuke Miyake, Yasuo Sato, Seiji Kajihara (KIT), Yukiya Miura (TMU) |
(77)
VLD |
14:55-15:20 |
A Scan-Out Power Reduction Method for Multi-Cycle BIST |
Senling Wang, Yasuo Sato, Seiji Kajihara, Kohei Miyase (Kyutech) |
(78)
DC |
15:20-15:45 |
A don't care filling method improve fault sensitization coverage on transition fault test set |
Ryosuke Wakasugi, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyusyu Univ) |
Wed, Nov 28 PM
16:00 - 17:15 |
(79)
DC |
16:00-16:25 |
A Method to Estimate the Number of Don't-Care Bits with Netlist |
Kohei Miyase, Seiji Kajihara, Xiaoqing Wen (KIT) |
(80)
DC |
16:25-16:50 |
A Study on Test Generation for Effective Test Compaction |
Yukino Kusuyama, Tatuya Yamazaki, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyusyu Univ.), Koji Yamazaki (Meiji Univ.) |
(81)
DC |
16:50-17:15 |
A Design Method of Fault-Secure Parallel Prefix Adders by Carry-Bit Duplication |
Nobutaka Kito (Chukyo Univ.), Naofumi Takagi (Kyoto Univ.) |
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