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=============================================== Technical Committee on Computer Systems (CPSY) Chair: Hideharu Amano (Keio Univ.) Vice Chair: Akira Asato (Fujitsu), Tsutomu Yoshinaga (Univ. of Electro-Comm.) Secretary: Hidetsugu Irie (Univ. of Electro-Comm.), Koji Nakano (Hiroshima Univ.) Assistant: Hiroaki Inoue (NEC) =============================================== Technical Committee on VLSI Design Technologies (VLD) Chair: Akihisa Yamada (Sharp) Vice Chair: Makoto Ikeda (Univ. of Tokyo) Secretary: Takashi Takenaka (NEC), Shigetoshi Nakatake (Univ. of Kitakyushu) =============================================== Technical Committee on Reconfigurable Systems (RECONF) Chair: Moritoshi Yasunaga (Univ. of Tsukuba) Vice Chair: Shorin Kyo (Renesas), Minoru Watanabe (Shizuoka Univ.) Secretary: Nobuya Watanabe (Okayama Univ.), Yutaka Yamada (Toshiba) Assistant: Yoshiki Yamaguchi (Univ. of Tsukuba) =============================================== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) Chair: Michiaki Muraoka (Kochi Univ.) Secretary: Hiroaki Komatsu (Fujitsu), Naoki Iwata (Sony), Nozomu Togawa (Waseda Univ.) DATE: Wed, Jan 16, 2013 09:10 - 18:15 Thu, Jan 17, 2013 09:10 - 16:05 PLACE: TOPICS: ---------------------------------------- Wed, Jan 16 AM (09:10 - 10:25) ---------------------------------------- (1)/RECONF 09:10 - 09:35 Architecture Evaluation of a Reconfigurable Device MPLD Tomoya Yamashita, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Takashi Ishiguro (TAIYO YUDEN) (2)/RECONF 09:35 - 10:00 A Design Method of Network-on-Chip Architecture for FPGA Hideki Katabami, Hiroshi Saito (Aizu Univ.) (3)/RECONF 10:00 - 10:25 A Study of 3D FPGA Architecture Using Face-to-Face Stacked Routing Layer Yusuke Iwai, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) ----- Break ( 10 min. ) ----- ---------------------------------------- Wed, Jan 16 AM (10:35 - 11:50) ---------------------------------------- (4)/RECONF 10:35 - 11:00 Performance Evaluation of Parametalized Data Compression Hardware for Floating-Point Data Stream Tomohiro Ueno, Yoshiaki Kono, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.) (5)/RECONF 11:00 - 11:25 An Architecture for IPv6 Lookup Using Parallel Index Generation Units Hiroki Nakahara (Kaoghima Univ.), Tsutomu Sasao, Munehiro Matsuura (KIT) (6)/RECONF 11:25 - 11:50 Implementation of a neural network for FPGA-based digital DC-DC converters Yoshihiko Yamabe, Masashi Motomura, Kentaro Yamashita, Hidenori Maruta, Yuichiro Shibata, Kiyoshi Oguri, Fujio Kurokawa (Nagasaki Univ.) ----- Lunch Break ( 70 min. ) ----- ---------------------------------------- Wed, Jan 16 PM (13:00 - 14:00) ---------------------------------------- (7)/CPSY 13:00 - 14:00 [Invited Talk] Challenges and Opportunities for Normally-Off Computing Hiroshi Nakamura (U. Tokyo) ----- Break ( 10 min. ) ----- ---------------------------------------- Wed, Jan 16 PM (14:10 - 15:25) ---------------------------------------- (8)/VLD 14:10 - 14:35 Optimal Design and Performance Evaluation of Residue Arithmetic Circuits with a Binary Coding of Signed-Digit Number Takuya Kobayashi, Kazuhiro Motegi, Shugang Wei (Gunma Univ.) (9)/VLD 14:35 - 15:00 Design and Performance Evaluation of RSA Encryption Processor Using Signed-Digit Number Arithmetic Junichi Asaoka, Yuuki Tanaka, Shugang Wei (Gunma Univ.) (10)/VLD 15:00 - 15:25 Automatic generation of the Power-Switch Driver Circuit and evaluation in Power-gating design implementation Makoto Miyauchi, Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.) ----- Break ( 10 min. ) ----- ---------------------------------------- Wed, Jan 16 PM (15:35 - 16:50) ---------------------------------------- (11)/VLD 15:35 - 16:00 Scaling the size of Expressions in Random Testing of Arithmetic Optimization of C Compilers Eriko Nagai, Atsushi Hashimoto, Nagisa Ishiura (Kwansei Gakuin Univ.) (12)/VLD 16:00 - 16:25 Break Even Time Evaluation of Run-Time Power Gating Control by On-chip Leakage Monitor Kensaku Matsunaga, Masaru Kudo (SIT), Yuya Ohta, Nao Konishi (SIT), Hideharu Amano (KU), Ryuichi Sakamoto, Mitaro Namiki (TUAT), Kimiyoshi Usami (SIT) (13)/VLD 16:25 - 16:50 Speeding up multiple sections of binary code by hardware accelerator tightly coupled with cpu Shunsuke Satake (Kwansei Gakuin Univ), Nagisa Ishiura, Shimpei Tamura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ), Hiroyuki Kanbara (ASTEM) ----- Break ( 10 min. ) ----- ---------------------------------------- Wed, Jan 16 PM (17:00 - 18:15) ---------------------------------------- (14)/VLD 17:00 - 17:25 Dynamic Multi-Vth Control Using Body Biasing in Silicon on Thin Buried Oxide (SOTB) Shinya Ajiro, Masaru Kudo, Kimiyoshi Usami (Shibaura Inst. of Tech.) (15)/VLD 17:25 - 17:50 An Improved Routing Method using Minimum Cost Flow for Routes with Target Wire Lengths Kazuo Yamane, Kunihiro Fujiyoshi (TUAT) (16)/VLD 17:50 - 18:15 The Rohm0.18um Chip Design Trial Using AllianceEDA Tool-set and Cell Library Based on Lambda Rule for Deep-submicron Process -- Trial of Place and Routing Tools -- Tatsuya Hosokawa, Naohiko Shimizu (Tokai Univ.) ---------------------------------------- Thu, Jan 17 AM (09:10 - 10:25) ---------------------------------------- (17)/CPSY 09:10 - 09:35 An accelerator with minimal data transferring using ring connections He Guan, Jun Yao, Yasuhiko Nakashima (NAIST) (18)/CPSY 09:35 - 10:00 Design and Implementation of Prioritized On-chip Network with Priority Inversion Avoidance Takumi Ishida, Daiki Yamazaki, Masakazu Taniguchi, Kazutoshi Suito, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.) (19)/CPSY 10:00 - 10:25 FPGA-based Implementation of Sliding-Window Aggregates over Disordered Data Streams Yasin Oge, Masato Yoshimi (Univ. of Electro-Comm.), Takefumi Miyoshi (e-trees), Hideyuki Kawashima (Univ. of Tsukuba), Hidetsugu Irie, Tsutomu Yoshinaga (Univ. of Electro-Comm.) ----- Break ( 10 min. ) ----- ---------------------------------------- Thu, Jan 17 AM (10:35 - 11:50) ---------------------------------------- (20)/CPSY 10:35 - 11:00 Low power packet transfer technique on distributed real-time systems Yusuke Kumura, Osamu Yoshizumi, Kazutoshi Suito, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.) (21)/CPSY 11:00 - 11:25 Comparison between single host multi-GPU system with ExpEther and multi host system Shimpei Nomura, Tetsuya Nakahama (Keio Univ.), Junichi Higuchi, Yuki Hayashi, Takashi Yoshikawa (NEC), Hideharu Amano (Keio Univ.) (22)/CPSY 11:25 - 11:50 Low latency network topology using multiple links at each host Ryuta Kawano (Keio Univ.), Ikki Fujiwara (NII), Hiroki Matsutani, Hideharu Amano (Keio Univ.), Michihiro Koibuchi (NII) ----- Lunch Break ( 70 min. ) ----- ---------------------------------------- Thu, Jan 17 PM (13:00 - 14:15) ---------------------------------------- (23)/RECONF 13:00 - 13:25 A design of a line buffer module for image proccessing as a library of a high-level synthesis environment Naohisa Arakawa, Tomonori Izumi (Ritsumeikan Univ.) (24)/RECONF 13:25 - 13:50 A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs Krzysztof Jozwik, Shinya Honda, Masato Edahiro (Nagoya Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroaki Takada (Nagoya Univ.) (25)/RECONF 13:50 - 14:15 The method for automation of design verification using UML diagram Daiki Kano (Tokai Univ.), Naohiko Shimizu (Tokai Univ./IP ARCH, Inc.) ----- Break ( 10 min. ) ----- ---------------------------------------- Thu, Jan 17 PM (14:25 - 16:05) ---------------------------------------- (26)/RECONF 14:25 - 14:50 Implementation of a pupil detection method using an FPGA accelerator and a high-level synthesis tool Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) (27)/RECONF 14:50 - 15:15 Implementation of 3-D stencil computation with an FPGA accelerator and a high level synthesis tool Yoshihiro Nakamura, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) (28)/RECONF 15:15 - 15:40 Design and Implementation of High Performance Stencil Computer by using Mesh Connected FPGA Arrays Ryohei Kobayashi, Shinya Takamaeda-Yamazaki, Kenji Kise (Tokyo Tech) (29)/RECONF 15:40 - 16:05 Implementation and performance evaluation of the accelerator for Lattice Boltzmann method on FPGA cluster Yoshiaki Kono, Hayato Suzuki, Ryotaro Chiba, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.) # Information for speakers General Talk will have 20 minutes for presentation and 5 minutes for discussion. === Technical Committee on Computer Systems (CPSY) === # FUTURE SCHEDULE: Wed, Mar 13, 2013 - Thu, Mar 14, 2013: [Mon, Jan 14] Fri, Apr 26, 2013: [Thu, Feb 14] # SECRETARY: Akira ASATO (FUJITSU) TEL +81-44-754-3233, FAX +81-44-754-3214 E-mail: a          === Technical Committee on VLSI Design Technologies (VLD) === # FUTURE SCHEDULE: Mon, Mar 4, 2013 - Wed, Mar 6, 2013: Okinawa Seinen Kaikan [Fri, Dec 7], Topics: Design Technology for System-on-Silicon # SECRETARY: Takeshi Takenaka (NEC) E-mail:     aj cTel: 044-431-7194 # ANNOUNCEMENT: # See also VLD's homepage: http://www.ieice.org/~vld/ === Technical Committee on Reconfigurable Systems (RECONF) === # SECRETARY: Shorin Kyo (Okayama Univ.) E-mail: s   nk wz sTEL: +81-44-435-5446 === Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) === # FUTURE SCHEDULE: Wed, Mar 13, 2013 - Thu, Mar 14, 2013: [Mon, Jan 14] # SECRETARY: Nozomu Togawa (Waseda University) Email sldm2012 g     # ANNOUNCEMENT: # Please see the IPSJ-SLDM page below: http://www.sig-sldm.org/ Last modified: 2013-01-11 12:58:42 |
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