Mon, Mar 3 PM
13:00 - 14:15 |
| (1) |
13:00-13:25 |
Characterization of Random Telegraph Noise using Inhomogeneous Ring Oscillator |
Shohei Nishimura, Takashi Matsumoto (Kyoto Univ.), Kazutoshi Kobayashi (Kyoto Inst. of Tech.), Hidetoshi Onodera (Kyoto Univ.) |
| (2) |
13:25-13:50 |
Impact of CMOS Transistor Random Telegraph Noise on Combinational Circuit Delay |
Takashi Matsumoto (Kyoto Univ.), Kazutoshi Kobayashi (Kyoto Inst. of Tech.), Hidetoshi Onodera (Kyoto Univ.) |
| (3) |
13:50-14:15 |
Fast Simulation of Multilayered Power Distribution Networks by Using Conformal Mesh Model and Block-Type Leapfrog Scheme |
Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.) |
| |
14:15-14:30 |
Break ( 15 min. ) |
Mon, Mar 3 PM
14:30 - 15:20 |
| (4) |
14:30-14:55 |
nMOS Dynamic Shift Registers for Driver Circuit of Small LCD and Their Evaluations |
Shinji Higa, Tomohiro Kurita, Shuji Tsukiyama (Chuo Univ.) |
| (5) |
14:55-15:20 |
On a Statistical Method for Analyzing Lifetime of Series-Connected Batteries |
Daisuke Sasaki, Shuji Tsukiyama, Mariko Matsunaga (Chuo Univ.), Shingo Takahashi (NEC) |
| |
15:20-15:35 |
Break ( 15 min. ) |
Mon, Mar 3 PM
15:35 - 16:50 |
| (6) |
15:35-16:00 |
Improved scan-based side-channel attack on the LED block cipher independent of scan structure |
Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) |
| (7) |
16:00-16:25 |
Latch-based AES Encryption Circuit Against Fault Analysis |
Youhua Shi, Hiroaki Taniguchi, Nozomu Togawa, Masao Yanagisawa (Waseda Univ.) |
| (8) |
16:25-16:50 |
Secure scan design using improved random order scans and its evaluations |
Masaru Oya, Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) |
Tue, Mar 4 AM
09:15 - 10:30 |
| (9) |
09:15-09:40 |
An Enhancement of Length Difference Reduction Algorithm for Set Pair Routing |
Yusaku Yamamoto, Atsushi Takahashi (Tokyo Inst. of Tech.) |
| (10) |
09:40-10:05 |
An Effective Solution Space for Simulated Annealing |
Hiroshi Tezuka, Kunihiro Fujiyoshi (TUAT) |
| (11) |
10:05-10:30 |
Parallel Tabu Search for the Motif Extraction Problem in Molecular Biology and its GPGPU Implementation |
Yuki Tanihara, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.) |
| |
10:30-10:45 |
Break ( 15 min. ) |
Tue, Mar 4 AM
10:45 - 12:00 |
| (12) |
10:45-11:10 |
An Approach of Rate-Distortion Optimized Quantization and its Evaluation |
Genki Moriguchi, Hajime Sawano, Takashi Kambe (Kinki Univ.), Gen Fujita (Osaka Electro-Comm. Univ.) |
| (13) |
11:10-11:35 |
An Hardware Implementation of Motion Estimation Technology Using High Level Synthesis |
Shota Nagai, Takashi Kambe (Kinki Univ.), Gen Fujita (Osaka Electro-Comm. Univ.) |
| (14) |
11:35-12:00 |
Effect of Correlated Stochastic Numbers on Calculation Accuracy |
Shota Ishii, Daiki Sunamori, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.) |
| |
12:00-13:20 |
Lunch ( 80 min. ) |
Tue, Mar 4 PM
13:20 - 13:45 |
| (15) |
13:20-13:45 |
[Invited Talk]
Advanced Model-Based Hotspot Fix Flow for Layout Optimization with Genetic Algorithm |
Shuhei Sota (Toshiba Microelectronics), Taiga Uno, Masanari Kajiwara, Chikaaki Kodama (Toshiba), Hirotaka Ichikawa (Toshiba Microelectronics), Ryota Aburada, Toshiya Kotani (Toshiba), Kei Nakagawa, Tamaki Saito (Toshiba Microelectronics) |
| |
13:45-13:50 |
Break ( 5 min. ) |
Tue, Mar 4 PM
13:50 - 15:30 |
| (16) |
13:50-14:15 |
Local Pattern Modification Method for Lithographical ECO in Double Patterning |
Yutaro Miyabe, Atsushi Takahashi, Tomomi Matsui (Tokyo Inst. of Tech.), Yukihide Kohira (Univ. of Aizu), Yoko Yokoyama (Toshiba) |
| (17) |
14:15-14:40 |
Self-Aligned Double Patterning-Aware Modified Two-color Grid Routing |
Takeshi Ihara, Atsushi Takahashi (Tokyo Inst. of Tech.), Chikaaki Kodama (TOSHIBA) |
| (18) |
14:40-15:05 |
Self-Aligned Double and Quadruple Patterning-Aware Grid Routing |
Chikaaki Kodama (Toshiba), Hirotaka Ichikawa (Toshiba Microelectronics), Fumiharu Nakajima, Koichi Nakayama, Shigeki Nojima, Toshiya Kotani (Toshiba) |
| (19) |
15:05-15:30 |
Exposure source optimization by clustering for lithography |
Masashi Tawada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.), Takaki Hashimoto, Keishi Sakanushi, Shigeki Nojima, Toshiya Kotani (Toshiba) |
| |
15:30-15:45 |
Break ( 15 min. ) |
Tue, Mar 4 PM
15:45 - 17:00 |
| (20) |
15:45-16:10 |
[Memorial Lecture]
A Network-Flow-Based Optimal Sample Preparation Algorithm for Digital Microfluidic Biochips |
Trung Anh Dinh, Shigeru Yamashita (Ritsumeikan Univ.), Tsung-Yi Ho (National Cheng-Kung Univ.) |
| (21) |
16:10-16:35 |
[Memorial Lecture]
Co-simulation Framework for Streamlining Microprocessor Development on Standard ASIC Design Flow |
Tomoyuki Nakabayashi, Tomoyuki Sugiyama, Takahiro Sasaki (Mie Univ.), Eric Rotenberg (NCSU), Toshio Kondo (Mie Univ.) |
| (22) |
16:35-17:00 |
[Memorial Lecture]
HIE-Block Latency Insertion Method for Fast Transient Simulation of Nonuniform Multiconductor Transmission Lines |
Takahiro Takasaki, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.) |
Wed, Mar 5 AM
10:00 - 11:40 |
| (23) |
10:00-10:25 |
Area-Efficient Soft-Error Tolerant Datapath Design Based on Aggressive Resource Sharing |
Junghoon Oh, Mineo Kaneko (JAIST) |
| (24) |
10:25-10:50 |
Evaluation of Multiple Cell Upsets Considering Parasitic Bipolar Effects |
Jun Furuta (Kyoto Univ.), Kazutoshi Kobayashi (Kyoto Inst. of Tech.), Hidetoshi Onodera (Kyoto Univ.) |
| (25) |
10:50-11:15 |
Analysis of Radiation-Induced Errors in PLL based on Behavioral Modeling |
SinNyoung Kim (Kyoto Univ.), Tomohiro Fujita (Ritsumeikan Univ.), Akira Tsuchiya, Hidetoshi Onodera (Kyoto Univ.) |
| (26) |
11:15-11:40 |
Inductive-Coupling Interface for Multiple-Memory Chip Stacking |
Mitsuko Saito, Tadahiro Kuroda (Keio Univ.) |
| |
11:40-13:00 |
Lunch ( 80 min. ) |
Wed, Mar 5 PM
13:00 - 14:40 |
| (27) |
13:00-13:25 |
Investigation of thermal monitor for applying to Dynamic Voltage Scaling in SOTB |
Tatsuya Wada, Kimiyoshi Usami (Shibaura Inst. of Tech) |
| (28) |
13:25-13:50 |
Experiment and Analysis on Temperature Dependence of Delay and Energy for Subthreshold Circuits |
Hiroki Kushida, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech.), Masao Yanagisawa (Waseda Univ.) |
| (29) |
13:50-14:15 |
Design methodology on Dynamic Multi-Vth control technique for Silicon on Thin Buried Oxide(SOTB) |
Tatsuki Saigusa, Kimiyoshi Usami (Shibaura Inst. of Tech) |
| (30) |
14:15-14:40 |
Post –Silicon Tuning of Body Biasing and Clock Skew for Low-Voltage LSI |
Tatsunori Kubo, Mineo Kaneko (JASIT) |
| |
14:40-14:55 |
Break ( 15 min. ) |
Wed, Mar 5 PM
14:55 - 16:35 |
| (31) |
14:55-15:20 |
A Design Method of Mixed Synchronous-Asynchronous Circuit |
Kotaro Kato, Mineo Kaneko (JAIST) |
| (32) |
15:20-15:45 |
Function Code Extraction from RTL Property for Reuse |
Msaato Tatsuoka, Toshiaki Aoki, Mineo Kaneko (JAIST) |
| (33) |
15:45-16:10 |
A Case Study of Symbolic Model Checking for Verilog-HDL Hardware Design |
Tomoyuki Yokogawa, Daichi Higashiyama (Okayama Pref. Univ.), Masafumi Kondo (Kawasaki Univ. of Medical Welfare), Yoichiro Sato, Kazutami Arimoto (Okayama Pref. Univ.) |
| (34) |
16:10-16:35 |
Implementation of General-Synchronous Circuits into FPGA using Multi-Domain Clock Skew Scheduling |
Tatsuya Masui, Yukihide Kohira (Univ. of Aizu) |
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