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=============================================== Technical Committee on VLSI Design Technologies (VLD) Chair: Nozomu Togawa (Waseda Univ.) Vice Chair: Daisuke Fukuda (Fujitsu Labs.) Secretary: Yukihide Kohira (Univ. of Aizu), Yuichi Sakurai (Hitachi) Assistant: Kazuki Ikeda (Hitachi) =============================================== Technical Committee on Computer Systems (CPSY) Chair: Hidetsugu Irie (Univ. of Tokyo) Vice Chair: Michihiro Koibuchi (NII), Kota Nakajima (Fujitsu Lab.) Secretary: Tomoaki Tsumura (Nagoya Inst. of Tech.), Shinya Takameda (Hokkaido Univ.) Assistant: Eiji Arima (Univ. of Tokyo), Shugo Ogawa (Hitachi) =============================================== Technical Committee on Reconfigurable Systems (RECONF) Chair: Yuichiro Shibata (Nagasaki Univ.) Vice Chair: Kentaro Sano (RIKEN), Yoshiki Yamaguchi (Tsukuba Univ.) Secretary: Kazuya Tanigawa (Hiroshima City Univ.), Takefumi Miyoshi (e-trees.Japan) Assistant: Yuuki Kobayashi (NEC), Hiroki Nakahara (Tokyo Inst. of Tech.) =============================================== Special Interest Group on System Architecture (IPSJ-ARC) Chair: Hiroshi Inoue (Kyushu Univ.) Secretary: Masaaki Kondo (Univ. of Tokyo), Ryota Shioya (Nagoya Univ.), Miho Tanaka (Fujitsu Labs.), Yohei Hasegawa (Toshiba Memory) =============================================== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) Chair: Yutaka Tamiya (Fujitsu Lab.) Secretary: Akira Tsuchiya (Univ. Shiga Prefecture), Hiroe Iwasaki (NTT), Toru Sasaki (Mitsubishi Electric) DATE: Wed, Jan 22, 2020 11:00 - 18:10 Thu, Jan 23, 2020 09:30 - 20:30 Fri, Jan 24, 2020 09:30 - 17:05 PLACE: (https://www.keio.ac.jp/en/maps/hiyoshi.html) TOPICS: FPGA Applications, etc. ---------------------------------------- Wed, Jan 22 AM (11:00 - 12:15) ---------------------------------------- (1)/RECONF 11:00 - 11:25 Honda Koki, Wei Kaijie (Keio Univ.), Arai Masatoshi (Saitama Univ.), Amano Hideharu (Keio Univ.) (2)/RECONF 11:25 - 11:50 Task offloading from vector processor to FPGA through PCIe connection Kohei Hijikata (Tohoku Univ.), Tomohiro Ueno (RIKEN), Ryusuke Egawa, Hiroyuki Takizawa (Tohoku Univ.), Kentaro Sano (RIKEN) (3)/RECONF 11:50 - 12:15 DDR4 SDRAM controller for real-time processing So Haramura, Nobuyuki Yamasaki (Keio Univ.) ----- Lunch Break ( 75 min. ) ----- ---------------------------------------- Wed, Jan 22 PM (13:30 - 15:10) ---------------------------------------- (4)/CPSY 13:30 - 13:55 A Consideration of NAT Traversal Function for MPI Runtime Environment on Android OS Masahiro Nissato, Kanemitsu Ootsu, Takashi Yokota (Utsunomiya Univ.) (5)/CPSY 13:55 - 14:20 (See Japanese page.) (6)/CPSY 14:20 - 14:45 Implementation and Evaluation of a Router on a Multi-FPGA System Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Yugo Yamauchi, Kazuei Hironaka, Hideharu Amano (Keio Univ.) (7)/CPSY 14:45 - 15:10 Performance Evaluation of Using Multi-Switch on a Multi-FPGA System Kohei Ito, Kensuke Iizuka, Yugo Yamauchi, Kazuei Hironaka (Keio Univ.), Yao Hu, Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) ----- Break ( 15 min. ) ----- ---------------------------------------- Wed, Jan 22 PM (15:25 - 16:40) ---------------------------------------- (8)/VLD 15:25 - 15:50 Increasing Test Variation for C Compilers by Equivalent Mutant Generation Hiroki Maeda, Nagisa ishiura (Kwansei Gakuin Univ.) (9)/VLD 15:50 - 16:15 Mutation Fuzzing Based on Type Estimation of Data Items Utilizing Data Writer Yoko Higuchi, Nagisa Ishiura, Namba Noriyuki (Kwansei Gakuin Univ.) (10)/VLD 16:15 - 16:40 On logic locking method with affine transformation Yusuke Matsunaga (Kyushu Univ.) ----- Break ( 15 min. ) ----- ---------------------------------------- Wed, Jan 22 PM (16:55 - 18:10) ---------------------------------------- (11)/RECONF 16:55 - 17:20 A Comparison of Filter for Convolutional Neural Network towards Hardware Implementation Kosuke Akimoto, Youki Sada, Shimpei Sato, Hiroki Hakahara (Tokyo Tech) (12)/RECONF 17:20 - 17:45 Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks Ryosuke Kuramochi, Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara (Titech) (13)/RECONF 17:45 - 18:10 An FPGA Implementation of Monocular Depth Estimation Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara (titech) ---------------------------------------- Thu, Jan 23 AM (09:30 - 10:45) ---------------------------------------- (14)/CPSY 09:30 - 09:55 An Efficient Cooperative Model Update using On-Device Learning Rei Ito, Mineto Tsukada, Hiroki Matsutani (Keio Univ.) (15)/CPSY 09:55 - 10:20 A Light-Weight Reinforcement Learning using Online Sequential Learning Hirohisa Watanabe, Mineto Tsukada, Hiroki Matsutani (Keio Univ.) (16) 10:20 - 10:45 ----- Break ( 15 min. ) ----- ---------------------------------------- Thu, Jan 23 AM (11:00 - 12:15) ---------------------------------------- (17)/VLD 11:00 - 11:25 Memory access optimization for convolution with scheduling transformations of dependence graphs Takayuki Todokoro, Kenshu Seto (TCU) (18)/VLD 11:25 - 11:50 Full Hardware Synthesis of FreeRTOS-Based Systems Wakako Nakano, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) (19)/VLD 11:50 - 12:15 Binary Synthesis from RISC-V Executables Shoki Hamana, Nagisa Ishiura (Kwansei Gakuin Univ.) ----- Lunch Break ( 75 min. ) ----- ---------------------------------------- Thu, Jan 23 PM (13:30 - 15:10) ---------------------------------------- (20)/RECONF 13:30 - 13:55 Design and implementation of a RISC-V computer system running Linux in Verilog HDL Junya Miura, Hiromu Miyazaki, Kenji Kise (Tokyo Tech) (21)/RECONF 13:55 - 14:20 Design and implementation of a RISC-V soft processor adopting five-stage pipelining Hiromu Miyazaki, Takuto Kanamori, Md Ashraful Islam, Kenji Kise (Tokyo Tech) (22)/RECONF 14:20 - 14:45 (See Japanese page.) (23)/RECONF 14:45 - 15:10 Study of a Simplified Digital Spiking Neuron and Its FPGA Implementation Tomohiro Yoneda (NII) ----- Break ( 15 min. ) ----- ---------------------------------------- Thu, Jan 23 PM (15:25 - 16:40) ---------------------------------------- (24)/CPSY 15:25 - 15:50 FPGA-based Stream Data Aggregation for Large Sliding-Windows Masaki Osaka (UEC), Masato Yoshimi (TIS), Celimuge Wu, Tsutomu Yoshinaga (UEC) (25)/CPSY 15:50 - 16:15 () (26)/CPSY 16:15 - 16:40 Accelerating 2D LiDAR SLAM Algorithm using FPGA Keisuke Sugiura, Hiroki Matsutani (Keio Univ.) ----- Break ( 15 min. ) ----- ---------------------------------------- Thu, Jan 23 PM (16:55 - 20:30) ---------------------------------------- (27)/CPSY 16:55 - 17:55 (See Japanese page.) ----- Break ( 35 min. ) ----- (28) 18:30 - 20:30 ---------------------------------------- Fri, Jan 24 AM (09:30 - 10:45) ---------------------------------------- (29)/RECONF 09:30 - 09:55 A Case Study of Development of Signal Processing Systems with RFSoC Ryohei Niwase (e-trees), Makoto Negoro, Yuta Kawai (Osaka Univ.), Takefumi Miyoshi (e-trees) (30)/RECONF 09:55 - 10:20 Quantum control of electron spin qubit with RFSoC Yuta Kawai, Takato Koide, Hiroki Imawaka, Koichiro Miyanishi (Osaka Univ.), Ryohei Niwase, Takefumi Miyoshi (e-trees), Makoto Negoro, Akinori Kagawa (Osaka Univ.) (31)/RECONF 10:20 - 10:45 Virtual-Channel Implementation on Communication Circuit of FPGA Cluster by Qsys Interconnect Naohisa Fukase, Akihisa Furuiti, Yasuyuki Miura, Tsukasa-Pierre Nakao (SIT) ----- Break ( 15 min. ) ----- ---------------------------------------- Fri, Jan 24 AM (11:00 - 12:15) ---------------------------------------- (32)/CPSY 11:00 - 11:25 Parameter Aggregation using Software Switch for Multi-GPU Deep Learning Masaki Furukawa, Tomoya Itsubo, Hiroki Matsutani (Keio Univ.) (33)/CPSY 11:25 - 11:50 Implementation of high speed rainbow table generation using Keccak hashing algorithm on CUDA Nguyen Dat Thuong, Keisuke Iwai, Takashi Matsubara, Takakazu Kurokawa (NDA) (34)/CPSY 11:50 - 12:15 Prioritized Resource Management for Reservation Stations Shota Nakabeppu, Nobuyuki Yamasaki (Keio Univ.) ----- Lunch Break ( 75 min. ) ----- ---------------------------------------- Fri, Jan 24 PM (13:30 - 15:10) ---------------------------------------- (35)/VLD 13:30 - 13:55 An FPGA implementation of arc-sine high-radix CORDIC algorithm Hiroshi Matsuoka, Naofumi Takagi (Kyoto Univ.), Kazuyoshi Takagi (Mie Univ.) (36)/VLD 13:55 - 14:20 Edge detection algorithms using stochastic architectures for various images Naoto Shinozaki, Kimiyoshi Usami (SIT) (37)/VLD 14:20 - 14:45 An Approach to Approximate Multiplier Optimization Xinpei Zhang, Amir Masoud Gharehbaghi, Masahiro Fujita (Univ. Tokyo) (38)/VLD 14:45 - 15:10 Partial synthesis method based on Column-wise verification for integer multipliers Jian Gu, Amir Masoud Gharehbaghi, Masahiro Fujita (UTokyo) ----- Break ( 15 min. ) ----- ---------------------------------------- Fri, Jan 24 PM (15:25 - 17:05) ---------------------------------------- (39)/RECONF 15:25 - 15:50 Measuring SER by Neutron Irradiation Between Volatile SRAM-based and Nonvolatile Flash-based FPGAs Yuya Kawano, Yuto Tsukita, Jun Furuta, Kazutoshi Kobayashi (KIT) (40)/RECONF 15:50 - 16:15 (See Japanese page.) (41)/RECONF 16:15 - 16:40 (See Japanese page.) (42)/RECONF 16:40 - 17:05 Study of stacked type logic LSI with fabrication technology of 3D flash memory. Fumiya Suzuki, Shigeyoshi Watanabe (Shonan Inst of Tech.) # Information for speakers General Talk will have 20 minutes for presentation and 5 minutes for discussion. === Technical Committee on VLSI Design Technologies (VLD) === # FUTURE SCHEDULE: Wed, Mar 4, 2020 - Sat, Mar 7, 2020: Okinawa Ken Seinen Kaikan [Fri, Jan 17], Topics: Design Technology for System-on-Silicon, Hardware Security, etc. # SECRETARY: Yukihide Kohira (Univ. of Aizu) E-mail:     u-ai  # ANNOUNCEMENT: # See also VLD's homepage: http://www.ieice.org/~vld/ === Technical Committee on Computer Systems (CPSY) === # FUTURE SCHEDULE: Thu, Feb 27, 2020 - Fri, Feb 28, 2020: Yoron-cho Chuou-Kouminkan [Mon, Jan 6], Topics: ETNET 2020 # SECRETARY: CPSY WEB https://www.ieice.org/~cpsy/ === Technical Committee on Reconfigurable Systems (RECONF) === # SECRETARY: Masato Motomura（Hokkaido Univ.） E-mail:    ist    i# ANNOUNCEMENT: # http://www.ieice.org/~reconf/ === Special Interest Group on System Architecture (IPSJ-ARC) === # FUTURE SCHEDULE: Thu, Feb 27, 2020 - Fri, Feb 28, 2020: Yoron-cho Chuou-Kouminkan [Mon, Jan 6], Topics: ETNET 2020 === Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) === # FUTURE SCHEDULE: Thu, Feb 27, 2020 - Fri, Feb 28, 2020: Yoron-cho Chuou-Kouminkan [Mon, Jan 6], Topics: ETNET 2020 # SECRETARY: Akira Tsuchiya (The University of Shiga Prefecture) E-mail:    aeusp# ANNOUNCEMENT: # Please see the IPSJ-SLDM page below: http://www.sig-sldm.org/ Last modified: 2020-01-14 19:39:10 |
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