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=============================================== Technical Committee on Reconfigurable Systems (RECONF) Chair: Akira Nagoya (Okayama Univ.) Vice Chair: Tetsuo Hironaka (Hiroshima City Univ.), Shorin Kyo (Renesas) Secretary: Tomonori Izumi (Ritsumeikan Univ.), Yohei Hori (AIST) Assistant: Nobuya Watanabe (Okayama Univ.) DATE: Thu, May 13, 2010 13:30 - 18:10 Fri, May 14, 2010 09:30 - 14:30 PLACE: TOPICS: ---------------------------------------- Thu, May 13 PM (13:30 - 14:45) ---------------------------------------- (1) 13:30 - 13:55 FPGA Implementation of Fast Proportional Digital PID Control for DC-DC Converters Kazuma Hamawaki, Yuki Maeda, Masato Soejima, Yuichiro Shibata, Kiyoshi Oguri, Fujio Kurokawa (Nagasaki Univ.) (2) 13:55 - 14:20 An FPGA implementation of Full-search variable block size motion Estimation Shuichi Asano, Zhi Shun Zheng, Tsutomu Maruyama (Univ. of Tsukuba) (3) 14:20 - 14:45 Real-time processing of contrast limited adaptive histogram equalization on FPGA Kentaro Kokufuta, Tsutomu Maruyama (Univ. of Tsukuba) ----- Break ( 10 min. ) ----- ---------------------------------------- Thu, May 13 PM (14:55 - 16:10) ---------------------------------------- (4) 14:55 - 15:20 A study on multicore designed MuCCRA3 : dynamically reconfigurable processor array Eiichi Sasaki, Yoshiki Saito, Masayuki Kimura, Hideharu Amano (Keio Univ.) (5) 15:20 - 15:45 First Prototype Chip of a Non-Volatile Reconfigurable Logic using FeRAM Cells Masahiro Koga, Masahiro Iida, Motoki Amagasaki (Kumamoto Univ.), Yoshinobu Ichida, Mitsuro Saji, Jun Iida (ROHM), Toshinori Sueyoshi (Kumamoto Univ.) (6) 15:45 - 16:10 Digit-Serial Floating Point Unit for High Precision Scientific Computation Engine Kazuya Tanigawa, Taiga Ban, Tetsuo Hironaka (Hiroshima City Univ.) ----- Break ( 10 min. ) ----- ---------------------------------------- Thu, May 13 PM (16:20 - 17:10) ---------------------------------------- (7) 16:20 - 16:45 A Case Study of Evaluation Technique for Soft Error Tolerance on SRAMs-based FPGAs. Tsuyoshi Kimura, Noritaka Kai, Yoshiaki Tsutsumi, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) (8) 16:45 - 17:10 A datapath classification method for efficient arithmetic pipeline combining on FPGAs Yui Ogawa, Tomonori Ooya (Nagasaki Univ.), Yasunori Osana (Seikei Univ.), Masato Yoshimi (Doshisha Univ.), Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano (Keio Univ.), Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) ----- Break ( 10 min. ) ----- ---------------------------------------- Thu, May 13 PM (17:20 - 18:10) ---------------------------------------- (9) 17:20 - 18:10 [Invited Talk] Stream processing bring out performance of wired logic Kiyoshi Oguri (Nagasaki Univ.) ---------------------------------------- Fri, May 14 AM (09:30 - 10:45) ---------------------------------------- (10) 09:30 - 09:55 Detecting patterns in various size and angle using FPGA Masayuki Suzuki, Yoshifumi Tanida, Tsutomu Maruyama (Univ. of Tsukuba) (11) 09:55 - 10:20 An FPGA Implementation of Tracking Control System with Vibration Control Yasuaki Tezuka, Shuichi Ichikawa, Yoshiyuki Noda (TUT) (12) 10:20 - 10:45 A study of a single-instruction variable-data processor on an FPGA Syoji Tanabe, Yoshiki Yamaguchi, Moritoshi Yasunaga (Univ. of Tsukuba) ----- Break ( 10 min. ) ----- ---------------------------------------- Fri, May 14 AM (10:55 - 12:10) ---------------------------------------- (13) 10:55 - 11:20 Software-Hardware Communication and Remote Call on a PC-FPGA Hybrid Cluster Masaki Kohata, Akira Uejima, Ryo Ozaki (Okayama Univ. of Sci.) (14) 11:20 - 11:45 GALS Design for Scalable Array Processors Operating on Multiple FPGAs Wang Luzhou, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.) (15) 11:45 - 12:10 Evaluation using Multiple Different Applications of OS for an FPGA-based Reconfigurable System Akira Kojima, Kazuya Tokunaga, Tetsuo Hironaka (Hiroshima City Univ.) ----- Break ( 65 min. ) ----- ---------------------------------------- Fri, May 14 PM (13:15 - 14:30) ---------------------------------------- (16) 13:15 - 13:40 An Efficient Implementation of Exhaustive Verification of the Collatz Conjecture using DSP48E blocks of Xilinx Virtex-5 FPGAs Yasuaki Ito, Koji Nakano (Hiroshima Univ.) (17) 13:40 - 14:05 Implementation of Arithmetic Pipeline on FLOPS-2D:Multi-FPGA Platform Hirokazu Morishita, Kenta Inakagata (Keio Univ.), Yasunori Osana (Seikei Univ.), Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.) (18) 14:05 - 14:30 A translational system using dynamic reconfigurable processor Kei Kinoshita, Daisuke Takano, Tomoyuki Okamura, Tetsuhiko Yao, Yoshiki Yamaguchi (Univ. of Tsukuba) # Information for speakers General Talk will have 20 minutes for presentation and 5 minutes for discussion. === Technical Committee on Reconfigurable Systems (RECONF) === # SECRETARY: Nobuya WATANABE (Okayama Univ.) E-mail:  bu      -u TEL: +81-86-251-8251 FAX: +81-86-251-8251 Last modified: 2010-05-06 12:31:53 |
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