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=============================================== Special Interest Group on Computer Architecture (IPSJ-ARC) =============================================== Technical Committee on VLSI Design Technologies (VLD) Chair: Nagisa Ishiura (Kwansei Gakuin Univ.) Vice Chair: Kazutoshi Wakabayashi (NEC) Secretary: Hiroyuki Ochi (Kyoto Univ.), Ichiro Kohno (Renesas) =============================================== Technical Committee on Computer Systems (CPSY) Chair: Toshinori Sueyoshi (Kumamoto Univ.) Vice Chair: Syuuichi Sakai (Univ. of Tokyo), Yoshio Miki (Hitachi) Secretary: Morihiro Kuga (Kumamoto Univ.), Akira Asato (Fujitsu Labs.) Assistant: Hidetsugu Irie (Univ. of Tokyo) =============================================== Technical Committee on Dependable Computing (DC) Chair: Kazuhiko Iwasaki (Tokyo Metropolitan Univ.) Vice Chair: Tomohiro Yoneda (NII) Secretary: Masato Kitagami (Chiba Univ.), Michinobu Nakao (Renesas) =============================================== Technical Committee on Reconfigurable Systems (RECONF) Chair: Hideharu Amano (Keio Univ.) Vice Chair: Nobuki Kajihara (NEC), Akira Nagoya (Okayama Univ.) Secretary: Masahiro Iida (Kumamoto Univ.), Tomonori Izumi (Ritsumeikan Univ.) Assistant: Yohei Hori (AIST) =============================================== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) Chair: Hidetoshi Onodera Secretary: Isaro Utsumi, Yutaka Tamiya, Tohru Ishihara DATE: Tue, Nov 20, 2007 10:05 - 17:15 Wed, Nov 21, 2007 13:00 - 17:00 Thu, Nov 22, 2007 09:00 - 16:10 PLACE: TOPICS: Design Gaia 2007 ---A New Frontier in VLSI Design--- ---------------------------------------- Tue, Nov 20 AM (10:05 - 11:45) ---------------------------------------- (1)/DC 10:05 - 10:30 2-Step Test Data Compression using Scan FF with Two Pattern Testability Kentaroh Katoh, Kazuteru Namba, Hideo Ito (Chiba Univ.) (2)/DC 10:30 - 10:55 A Transition Delay Test Generation Method for Capture Power Reduction during At-Speed Scan Testing Tomoaki Fukuzawa, Kohei Miyase, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara (KIT) (3)/DC 10:55 - 11:20 An optimization of thru trees for test generation based on acyclical testability Kohsuke Morinaga, Nobuya Oka, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) (4)/IPSJ-SLDM 11:20 - 11:45 An Approximate Invariant Property Checking Using Term-Height Reduction for a Subset of First-Order Logic Hiroaki Shimizu, Kiyoharu Hamaguchi, Toshinobu Kashiwabara (Osaka Univ.) ---------------------------------------- Tue, Nov 20 AM (10:05 - 11:45) ---------------------------------------- (5)/IPSJ-SLDM 10:05 - 10:30 A Memory Management Technique for Energy Reduction in Multi-Task Embedded Applications Seiichiro Yamaguchi, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) (6)/IPSJ-SLDM 10:30 - 10:55 An ILP Model of Code Placement Problem for Minimizing the Energy Consumption in Embedded Processors Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) (7)/VLD 10:55 - 11:20 A process-variation-aware low-power technique using current control Kyun-dong Kim, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya (Univ. of Tokyo) (8)/VLD 11:20 - 11:45 Proposal of domino-RSL circuit which is resistant to Differential Power Analysis attack on cryptographic circuit Yoshinobu Toyoda, Kenta Kido, Yoshiaki Shitabayashi, Takeshi Fujino (Ritsumeikan Univ.) ----- Break ( 15 min. ) ----- ----- Poster Session (Event Hall) ( 180 min. ) ----- ----- Break ( 10 min. ) ----- ---------------------------------------- Tue, Nov 20 PM CPSY: Design and Verification for Computer Systems (15:10 - 17:15) ---------------------------------------- (9)/CPSY 15:10 - 15:35 A Method for Optimizing Communication Architecture on Network-on-Chip Considering Chip Size and Wiring Costs Daisuke Hayashi, Wataru Murai (Osaka Univ.), Akio Nakata (Hiroshima City Univ.), Tomoya Kitani, Keiichi Yasumoto (NAIST), Teruo Higashino (Osaka Univ.) (10)/CPSY 15:35 - 16:00 Development of Inter-module Communication Mechanism for Dynamically Reconfigurable System Tomoyuki Ishida, Taiichiro Yatsunami, Osamu Kawaguchi, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) (11)/CPSY 16:00 - 16:25 KNIVES: Internet Based Distributed Shared Demand Side Management System Akihiro Oda, Tomokazu Tachikawa, Tomohiko Handa (Keio Univ.), Junichi Ichimura (Tokyo Gas Ltd.), Hiroaki Nishi (Keio Univ.) (12)/CPSY 16:25 - 16:50 FTN Simulation Technology Based on Analysis of Frequency, Time and Noise for High-speed Serial Communication System Goichi Ono, Takashi Takemoto, Koji Fukuda, Fumio Yuki, Ryo Nemoto, Eiichi Suzuki, Masayoshi Yagyu, Hiroki Yamashita, Tatsuya Saito (Hitachi) (13)/CPSY 16:50 - 17:15 The Evaluation of High-speed Serial Communication System by Using FTN Simulation Technology Takashi Takemoto, Goichi Ono, Koji Fukuda, Fumio Yuki, Ryo Nemoto, Eiichi Suzuki, Masayoshi Yagyu, Hiroki Yamashita, Tatsuya Saito (Hitachi) ---------------------------------------- Tue, Nov 20 PM RECONF: Reconfigurable Systems 1 (Room 21) (15:10 - 16:50) ---------------------------------------- (14)/RECONF 15:10 - 15:35 A Development of the Auto mapping tool for embedded Programmable Logic matriX (ePLX) and the study of ePLX local architecture Kouta Ishibashi, Yoshiyuki Tanaka, Mitsutaka Matsumoto (Ritsumeikan Univ.), Hirofumi Nakano, Takenobu Iwao, Yoshihiro Okuno, Kazutami Arimoto (Renesas Technology), Masaya Yoshikawa (Meijo Univ.), Tomonori Izumi, Takeshi Fujino (Ritsumeikan Univ.) (15)/RECONF 15:35 - 16:00 A Study of Conection Block Structure and Implementation Methods of Multi-Input Functions for Variable Grain Logic Cell Kazunori Matsuyama, Ryoichi Yamaguchi, Yoshiaki Satou, Hiroshi Miura, Masahiro Koga, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) (16)/RECONF 16:00 - 16:25 Track Swapping on Critical Paths Utilizing Random Variations for FPGAs to Enhance Speed and Yield Yuuri Sugihara, Youhei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ.) (17)/RECONF 16:25 - 16:50 Retrieving 3D infomation with streamed template matching Hidenori Matsubayashi, Shinsuke Nino, Toru Aramaki, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ) ---------------------------------------- Tue, Nov 20 PM (15:10 - 16:50) ---------------------------------------- (18)/DC 15:10 - 15:35 Comparison of Standard Cell Non-linear Asynchronous Pipelines Chammika Mannakkara, Tomohiro Yoneda (NII) (19)/IPSJ-SLDM 15:35 - 16:00 An On-Chip Bus Architecture for Post-Fabrication Timing Calibration Masaki Yamaguchi, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) (20)/VLD 16:00 - 16:25 Proposal and Circuit Performance Evaluation of Mask-less Via Programmable Device VPEX for EB Direct Writing Masahide Kawarasaki, Akihiro Nakamura, Tomoaki Nishimoto, Yoshiaki Shitabayashi, Takeshi Fujino (Ritsumeikan Univ.) (21)/VLD 16:25 - 16:50 Initial Evaluation of FIR Filter Based on Digit-Serial Computation Yuhki Yamabe, Kazuya Tanigawa, Tetsuo Hironaka (HCU) ---------------------------------------- Wed, Nov 21 PM (13:00 - 14:00) ---------------------------------------- (22) 13:00 - 14:00 [Fellow Memorial Lecture] Social Information Infrastructure and Dependable VLSI Hiroto Yasuura (Kyushu Univ.) ----- Break ( 15 min. ) ----- ---------------------------------------- Wed, Nov 21 PM RECONF: Dynamic Reconfiguration (Room 21) (14:15 - 15:30) ---------------------------------------- (23)/RECONF 14:15 - 14:40 The technical comparison of Digital Media Processor and Dynamically Reconfigurable Processor Kazuo Yamada, Takao Naito (Fuji Xerox) (24)/RECONF 14:40 - 15:05 An approach to Place and Route challenges in Dynamic Reconfiguration Ryo Hidaka, Fuminori Kobayashi (Kyushu Inst. of Tech.), Minoru Watanabe (Shizuoka Univ.) (25)/RECONF 15:05 - 15:30 Redusing Overhead of transferring configuration data on Dynamically Reconfigurable Processor MuCCRA Takuro Nakamura, Yohei Hasegawa, Satoshi Tsutsumi, Hideharu Amano (Keio Univ.) ---------------------------------------- Wed, Nov 21 PM (14:15 - 15:30) ---------------------------------------- (26)/DC 14:15 - 14:40 A design method for easily testable multipliers adaptable to various structures of partial product addition Nobutaka Kito, Naofumi Takagi (Nagoya Univ.) (27)/DC 14:40 - 15:05 Thermal-Aware Test Scheduling with Cycle-Accurate Power Profiles and Test Partitioning Thomas Edison Yu, Tomokazu Yoneda (NAIST), Krishnendu Chakrabarty (Duke Univ.), Hideo Fujiwara (NAIST) (28)/DC 15:05 - 15:30 A Construction Method of Path Delay Fault Detectable Circuits Takashi Watanabe, Takeo Yoshida (Univ. of the Ryukyus) ----- Break ( 15 min. ) ----- ---------------------------------------- Wed, Nov 21 PM RECONF: Low-power Techniques (Room 21) (15:45 - 17:00) ---------------------------------------- (29)/RECONF 15:45 - 16:10 Architecture Exploration Method for Low-Power Dynamically Reconfigurable Processors Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tunbungheng, Hideharu Amano (Keio Univ.) (30)/RECONF 16:10 - 16:35 Power analysis on Dynamic Reconfigurable Processor Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi, Hideharu Amano (Keio Univ.) (31)/RECONF 16:35 - 17:00 A low power consumption processor with on-chip control mechanism using pipeline stage unification Katsuya Kimura, Ryotaro Kobayashi, Toshio Shimada (Nagoya Univ.) ---------------------------------------- Wed, Nov 21 PM (15:45 - 17:00) ---------------------------------------- (32)/VLD 15:45 - 16:10 A Resource Binding Method for Reducing Power Consumption of LSI Data Communications Hidekazu Seto, Kazuhito Ito (Saitama Univ.) (33)/VLD 16:10 - 16:35 Design of low energy array multipliers by reducing signal transitions in partial product accumulators Hirotaka Kawashima, Kazuhiro Nakamura, Naofumi Takagi, Kazuyoshi Takagi (Nagoya Univ.) (34)/VLD 16:35 - 17:00 A power masking multiplying circuit based on galois field for composite field AES Nobuyuki Kawahata, Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) ---------------------------------------- Thu, Nov 22 AM RECONF: Reconfigurable Systems 2 (Room 21) (09:00 - 10:15) ---------------------------------------- (35)/RECONF 09:00 - 09:25 Designing Soft Error Tolerant LUTs of SRAM-based FPGAs Kohei Satoyama, Takashi Nakada, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima (NAIST) (36)/RECONF 09:25 - 09:50 Performance evaluation of reconfigurable architecture based on digit-serial computation Takuro Uchida, Tetsuya Zuyama, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.) (37)/RECONF 09:50 - 10:15 An Implementation of Operating System Functions for a Reconfigurable System Akira Kojima, Kazuya Tokunaga, Tetsuo Hironaka (Hiroshima City Univ.) ---------------------------------------- Thu, Nov 22 AM (09:00 - 10:15) ---------------------------------------- (38)/IPSJ-SLDM 09:00 - 09:25 Comparison between STA and SSTA results in microprocessor design Noriyuki Ito, Hiroaki Komatsu, Hiroyuki Sugiyama, Naomi Bizen, Katsumi Iguchi, Yuji Yoshida (Fujitsu) (39)/VLD 09:25 - 09:50 A New Technique for Elimination of Irregular Data in Measured Values -- A Data Screening Technique Appling Skewness of Basic Statistic -- Shin-ichi Ohkawa, Hiroo Masuda (Renesas) (40)/VLD 09:50 - 10:15 A Study of Grid-Based Modeling of Spatially Correlated Manufacturing Variability for SSTA Shinyu Ninomiya, Masanori Hashimoto (Osaka Univ.) ----- Break ( 15 min. ) ----- ---------------------------------------- Thu, Nov 22 AM RECONF: Coding and Arithmetics (Room 21) (10:30 - 11:45) ---------------------------------------- (41)/RECONF 10:30 - 10:55 A Multi-Rate Compatible Irregular LDPC Decoder Enhancing Column Operation Parallelism Yuta Imai, Kazunori Shimizu, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) (42)/RECONF 10:55 - 11:20 Proposal of Optimization Design System for LDPC using FPGA Yukari Ishida, Hirotaka Nosato (Toho Univ.), Yosuke Iijima (Univ. of Tsukuba), Eiichi Takahashi (AIST), Tatsumi Furuya (Toho Univ.), Tetsuya Higuchi (AIST) (43)/RECONF 11:20 - 11:45 Design Methods for Radix Converters (4) -- RNS to Binary Conversion -- Yukihiro Iguchi (Meiji Univ.), Tsutomu Sasao (Kyutech) ---------------------------------------- Thu, Nov 22 AM (10:30 - 11:45) ---------------------------------------- (44)/VLD 10:30 - 10:55 Highly Extensible Base Processors for Short-term ASIP Design Hirofumi Iwato, Takuji Hieda, Hiroaki Tanaka (Osaka Univ.), Jun Sato (Tsuruoka NCT), Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) (45)/VLD 10:55 - 11:20 Complexities and Algorithms of Minimum-Delay Compensation Problems in Datapath Synthesis Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki (JAIST) (46)/VLD 11:20 - 11:45 A Schedule Improvement with Skew Control in Datapath Synthesis Takayuki Obata, Mineo Kaneko (JAIST) ----- Lunch Break ( 75 min. ) ----- ---------------------------------------- Thu, Nov 22 PM RECONF: Applications (Room 21) (13:00 - 14:15) ---------------------------------------- (47)/RECONF 13:00 - 13:25 Proposal for High-Speed Secure Network System using FPGA Hirotaka Nosato, Yukari Ishida (Toho Univ.), Yosuke Iijima (Univ. of Tsukuba), Eiichi Takahashi (AIST), Tatsumi Furuya (Toho Univ.), Tetsuya Higuchi (AIST) (48)/RECONF 13:25 - 13:50 Evaluation of a Data-Driven Architecture for a Stochastic Biochemical Simulator on an FPGA Masato Yoshimi, Yuri Nishikawa, Toshinori Kojima, Yasunori Osana, Akira Funahashi (Keio Univ.), Noriko Hiroi (EMBL-EBI), Yuichiro Shibata, Hideki Yamada (Nagasaki Univ.), Hiroaki Kitano (JST), Hideharu Amano (Keio Univ.) (49)/RECONF 13:50 - 14:15 A Study on General Purpose Self-Organizing Map Hardware Accelerator Hiroshi Araki, Masato Yoshimi, Yasunori Osana, Hideharu Amano (Keio Univ.) ---------------------------------------- Thu, Nov 22 PM (13:00 - 14:40) ---------------------------------------- (50)/IPSJ-SLDM 13:00 - 13:25 Necessary and Sufficient Conditions for Symmetry Placements Kunihiro Fujiyoshi, Chikaaki Kodama, Shinichi Koda (TUAT) (51)/VLD 13:25 - 13:50 Improved Method of Rectilinear Block Packing Based on O-Tree Representation Hidehiko Ukibe, Kunihiro Fujiyoshi (TUAT) (52)/IPSJ-SLDM 13:50 - 14:15 Parallel prefix adder synthesis based on Ling’s carry computation Taeko Matsunaga, Shinji Kimura (Waseda Univ.), Yusuke Matsunaga (Kyushu Univ.) (53)/VLD 14:15 - 14:40 An Efficient Behavioral Synthesis Method Considering Specialized Functional Units Tsuyoshi Sadakata, Yusuke Matsunaga (Kyushu Univ.) ----- Break ( 15 min. ) ----- ---------------------------------------- Thu, Nov 22 PM (14:30 - 15:45) ---------------------------------------- (54)/VLD 14:30 - 14:55 A Hardware Engine for Generation Deformed Map Akira Arahata, Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) (55)/VLD 14:55 - 15:20 An LDPC Decoder Based on the Min-Sum Algorithm for High Speed WLAN Systems Nozomu Hama, Hiroyuki Shimajiri, Takeo Yoshida (Univ. of the Ryukyus) (56)/IPSJ-SLDM 15:20 - 15:45 Area Recovery under Depth Constraint for Technology Mapping for LUT-based FPGAs Taiga Takata, Yusuke Matsunaga (Kyushu Univ.) ---------------------------------------- Thu, Nov 22 PM (14:55 - 16:10) ---------------------------------------- (57)/VLD 14:55 - 15:20 Cycle Partitioned Scheduling for Code Optimization of VLIW DSP Yuuki Masui, Nagisa Ishiura (Kwansei Gakuin Univ.) (58)/VLD 15:20 - 15:45 Retargetable Linear Assembler for VLIW Processor Satoshi Nogaito, Nagisa Ishiura (Kwansei Gakuin Univ.), Masaharu Imai (Osaka Univ.) (59)/VLD 15:45 - 16:10 Memory Assignment Method Considering Orders of Operands for Massively Parallel Fine-grained SIMD Processor Akira Kobashi, Ittetsu Taniguchi, Hiroaki Tanaka, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.), Kiyoshi Nakata (Renesas) === Special Interest Group on Computer Architecture (IPSJ-ARC) === === Technical Committee on VLSI Design Technologies (VLD) === # FUTURE SCHEDULE: Wed, Jan 16, 2008 - Thu, Jan 17, 2008: Hiyoshi Campus, Keio University [Mon, Nov 12], Topics: FPGA Applications, etc # SECRETARY: Hiroyuki OCHI (Kyoto Univ.) E-mail:o    ee k  -u Tel.075-753-4803 # ANNOUNCEMENT: # See also VLD's homepage: http://www.ieice.org/~vld/ === Technical Committee on Computer Systems (CPSY) === # FUTURE SCHEDULE: Wed, Dec 19, 2007: Campus Plaza Kyoto [Fri, Oct 26], Topics: Interconnect technology, etc Wed, Jan 16, 2008 - Thu, Jan 17, 2008: Hiyoshi Campus, Keio University [Mon, Nov 12], Topics: FPGA Applications, etc # SECRETARY: Morihiro KUGA (Kumamoto Univ.) TEL +81-96-342-3647, FAX +81-96-342-3599 E-mail:   am -u=== Technical Committee on Dependable Computing (DC) === # FUTURE SCHEDULE: Fri, Dec 7, 2007: [Mon, Sep 24] Fri, Feb 8, 2008: Kikai-Shinko-Kaikan Bldg. [Fri, Dec 14] # SECRETARY: Masato Kitakami Graduate School of Integration Science, Chiba University 1-33 Yayoi-cho Inage-ku, Chiba 263-8522 JAPAN TEL/FAX +42.290.3269 E-mail:    f ultyba-u === Technical Committee on Reconfigurable Systems (RECONF) === # FUTURE SCHEDULE: Wed, Jan 16, 2008 - Thu, Jan 17, 2008: Hiyoshi Campus, Keio University [Mon, Nov 12], Topics: FPGA Applications, etc # SECRETARY: Yohei HORI (AIST) E-mail:   yaist TEL: +81-29-861-5080 (Ext.)55459 FAX: +81-29-861-5909 === Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) === # FUTURE SCHEDULE: Wed, Jan 16, 2008 - Thu, Jan 17, 2008: Hiyoshi Campus, Keio University [Mon, Nov 12], Topics: FPGA Applications, etc Last modified: 2007-11-15 15:41:00 |
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