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Chair |
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Kentaro Sano (RIKEN) |
Vice Chair |
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Yoshiki Yamaguchi (Tsukuba Univ.), Tomonori Izumi (Ritsumeikan Univ.) |
Secretary |
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Yuuki Kobayashi (NEC), Yukinori Sato (Toyohashi Univ. of Tech.) |
Assistant |
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Yukitaka Takemura (INTEL), Yasunori Osana (Ryukyu Univ.) |
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Conference Date |
Wed, Sep 7, 2022 13:00 - 18:00
Thu, Sep 8, 2022 09:45 - 14:20 |
Topics |
Reconfigurable system, etc. |
Conference Place |
emCAMPUS. and Zoom |
Address |
2-81 Ekimaeohdohri, Toyohashi-shi, Aichi 440-0888 |
Notes on Review |
This article is a technical report without peer review, and its polished version will be published elsewhere. |
Registration Fee |
This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on RECONF. |
Wed, Sep 7 PM 13:00 - 13:50 |
(1) |
13:00-13:50 |
[Invited Talk]
Domain specific accelerators optimized for next-generation embedded systems |
Teppei Hirotsu (NSITEXE) |
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13:50-14:10 |
Break ( 20 min. ) |
Wed, Sep 7 PM 14:10 - 15:00 |
(2) |
14:10-14:35 |
Efficient Learning of Spiking Neural Networks with Genetic Algorithm and its FPGA Acceleration |
Taiki Watanabe, Yukinori Sato (TUT) |
(3) |
14:35-15:00 |
Simulation for a CNN implementation on a multi-FPGA system with system-C description |
Shao Ningyu, Hiroaki Suzuki (Keio Univ.), Wataru Takahashi (NEC), Kazutoshi Wakabayashi (Tokyo Univ.), Hideharu Amano (Keio Univ.) |
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15:00-15:20 |
Break ( 20 min. ) |
Wed, Sep 7 PM 15:20 - 16:10 |
(4) |
15:20-15:30 |
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(5) |
15:30-15:40 |
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(6) |
15:40-15:50 |
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(7) |
15:50-16:00 |
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(8) |
16:00-16:10 |
[Short Paper]
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Zuquan Qin, Weu Kaijie, Hideharu Amano (Keio Univ.), Kazuhiro Nakadai (TIT) |
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16:10-16:20 |
LT Q&A ( 10 min. ) |
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16:20-16:30 |
Break ( 10 min. ) |
Wed, Sep 7 PM 16:30 - 18:00 |
(9) |
16:30-18:00 |
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Thu, Sep 8 AM 09:45 - 11:00 |
(1) |
09:45-10:10 |
FPGA implementation of small area sum-of-products arithmetic unit for Posit and consideration of its introduction into AI chip ReNA |
Yasuhiro Nakahara, Yuta Masuda, Masato Kiyama, Masahiro Iida (Kumamoto Univ.) |
(2) |
10:10-10:35 |
Proposal and evaluation of Combined Posit MAC unit (CPMAC) for both DNN inference and training |
Yuta Masuda, Yasuhiro Nakahara, Masato Kiyama, Masahiro Iida (Kumamoto Univ.) |
(3) |
10:35-11:00 |
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11:00-11:20 |
Break ( 20 min. ) |
Thu, Sep 8 AM 11:20 - 12:10 |
(4) |
11:20-11:45 |
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(5) |
11:45-12:10 |
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Thu, Sep 8 PM 12:10 - 12:10 |
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12:10-12:30 |
( 20 min. ) |
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12:30-13:40 |
Break ( 70 min. ) |
Thu, Sep 8 PM 13:40 - 14:20 |
(6) |
13:40-13:50 |
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(7) |
13:50-14:00 |
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Takuya Kojima, Kaito Kokubu, Makoto Saito, Yuna Tomida, Shion Maeda (UTokyo) |
(8) |
14:00-14:10 |
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(9) |
14:10-14:20 |
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14:20-14:30 |
LT Q&A ( 10 min. ) |
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15:00-16:30 |
( 90 min. ) |
Announcement for Speakers |
General Talk | Each speech will have 20 minutes for presentation and 5 minutes for discussion. |
Last modified: 2022-09-05 19:07:39
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