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=============================================== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) Chair: Michiaki Muraoka (Kochi Univ.) Secretary: Naoki Iwata (Sony), Koutarou Shimamura (Hitachi), Makoto Sugihara (Kyushu U) =============================================== Technical Committee on VLSI Design Technologies (VLD) Chair: Makoto Ikeda (Univ. of Tokyo) Vice Chair: Toshiyuki Shibuya (Fujitsu Labs.) Secretary: Shigetoshi Nakatake (Univ. of Kitakyushu), Noriyuki Minegishi (Mitsubishi Electric) DATE: Wed, May 28, 2014 Thu, May 29, 2014 08:30 - 16:30 PLACE: Kitakyushu International Conference Center(Dr. Makoto Sugihara) TOPICS: System Design, etc. ---------------------------------------- Thu, May 29 AM (08:30 - 09:45) ---------------------------------------- (1)/VLD 08:30 - 08:55 Analog Floorplan with Hierarchical Structure Constraints Shigetoshi Nakatake (Univ. of Kitakyushu) (2)/VLD 08:55 - 09:20 Characteristics of Programmable Delay Element based on Channel Decomposition Daijiro Murooka, Koji Nagao, Yu Zhang, Shigetoshi Nakatake (Univ. of Kitakyushu) (3)/VLD 09:20 - 09:45 A Subgradient Method for Analytical Minimization of Half-Perimeter Wirelength Sohta Kayama, Hiroshi Miyashita (Univ. of Kitakyushu) ----- Break ( 10 min. ) ----- ---------------------------------------- Thu, May 29 AM (09:55 - 10:55) ---------------------------------------- (4)/VLD 09:55 - 10:55 [Invited Talk] Multiple Patterning Lithography by Positive Semidefinite Relaxation Tomomi Matsui (TITECH) ----- Break ( 10 min. ) ----- ---------------------------------------- Thu, May 29 AM (11:05 - 11:55) ---------------------------------------- (5)/VLD 11:05 - 11:30 Proposal of a Synthesis Flow for Asynchronous Circuits with Bundled-Data Implementation from a SystemC Model Taichi Komine, Hiroshi Saito (Univ. of Aizu) (6)/VLD 11:30 - 11:55 LELECUT Triple Patterning Lithography Layout Decomposition using Positive Semidefinite Relaxation Yukihide Kohira (Univ. of Aizu), Tomomi Matsui (Tokyo Tech), Yoko Yokoyama, Chikaaki Kodama (Toshiba), Atsushi Takahashi (Tokyo Tech), Shigeki Nojima, Satoshi Tanaka (Toshiba) ----- Break ( 90 min. ) ----- ---------------------------------------- Thu, May 29 PM (13:25 - 15:05) ---------------------------------------- (7)/VLD 13:25 - 13:50 Error Tolerance of Dual Pipeline Self Synchronous Circuits Sai Denki, Makoto Ikeda (Univ. of Tokyo) (8)/VLD 13:50 - 14:15 SOTB 65nm CMOS Design of Gate-Level Dual Pipeline Self-Synchronous Wallace Tree Multiplier Masato Tamura, Makoto Ikeda (Univ. of Tokyo) (9) 14:15 - 14:40 (10) 14:40 - 15:05 ----- Break ( 10 min. ) ----- ---------------------------------------- Thu, May 29 PM (15:15 - 16:30) ---------------------------------------- (11)/VLD 15:15 - 15:40 An Automatic Nested Loop Pipelining Method and Its Evaluation Yusuke Nakatsuji, Masahiro Nambu, Takashi Kambe (Kinki Univ.) (12) 15:40 - 16:05 (13) 16:05 - 16:30 # Information for speakers General Talk will have 20 minutes for presentation and 5 minutes for discussion. === Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) === # SECRETARY: Makoto Sugihara (Kyushu U) Email sldm2013   c aitk shu-u # ANNOUNCEMENT: # Please see the IPSJ-SLDM page below: http://www.sig-sldm.org/ === Technical Committee on VLSI Design Technologies (VLD) === # FUTURE SCHEDULE: Wed, Jul 9, 2014 - Fri, Jul 11, 2014: Hokkaido University [Fri, May 16], Topics: System, signal processing and related topics # SECRETARY: Shigetoshi Nakatake (Kitakyushu U) E-mail:      k-u# ANNOUNCEMENT: # See also VLD's homepage: http://www.ieice.org/~vld/ Last modified: 2014-04-16 17:36:10 |
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