Thu, May 29 AM 08:30 - 09:45 |
(1) VLD |
08:30-08:55 |
Analog Floorplan with Hierarchical Structure Constraints |
Shigetoshi Nakatake (Univ. of Kitakyushu) |
(2) VLD |
08:55-09:20 |
Characteristics of Programmable Delay Element based on Channel Decomposition |
Daijiro Murooka, Koji Nagao, Yu Zhang, Shigetoshi Nakatake (Univ. of Kitakyushu) |
(3) VLD |
09:20-09:45 |
A Subgradient Method for Analytical Minimization of Half-Perimeter Wirelength |
Sohta Kayama, Hiroshi Miyashita (Univ. of Kitakyushu) |
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09:45-09:55 |
Break ( 10 min. ) |
Thu, May 29 AM 09:55 - 10:55 |
(4) VLD |
09:55-10:55 |
[Invited Talk]
Multiple Patterning Lithography by Positive Semidefinite Relaxation |
Tomomi Matsui (TITECH) |
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10:55-11:05 |
Break ( 10 min. ) |
Thu, May 29 AM 11:05 - 11:55 |
(5) VLD |
11:05-11:30 |
Proposal of a Synthesis Flow for Asynchronous Circuits with Bundled-Data Implementation from a SystemC Model |
Taichi Komine, Hiroshi Saito (Univ. of Aizu) |
(6) VLD |
11:30-11:55 |
LELECUT Triple Patterning Lithography Layout Decomposition using Positive Semidefinite Relaxation |
Yukihide Kohira (Univ. of Aizu), Tomomi Matsui (Tokyo Tech), Yoko Yokoyama, Chikaaki Kodama (Toshiba), Atsushi Takahashi (Tokyo Tech), Shigeki Nojima, Satoshi Tanaka (Toshiba) |
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11:55-13:25 |
Break ( 90 min. ) |
Thu, May 29 PM 13:25 - 15:05 |
(7) VLD |
13:25-13:50 |
Error Tolerance of Dual Pipeline Self Synchronous Circuits |
Sai Denki, Makoto Ikeda (Univ. of Tokyo) |
(8) VLD |
13:50-14:15 |
SOTB 65nm CMOS Design of Gate-Level Dual Pipeline Self-Synchronous Wallace Tree Multiplier |
Masato Tamura, Makoto Ikeda (Univ. of Tokyo) |
(9) |
14:15-14:40 |
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(10) |
14:40-15:05 |
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15:05-15:15 |
Break ( 10 min. ) |
Thu, May 29 PM 15:15 - 16:30 |
(11) VLD |
15:15-15:40 |
An Automatic Nested Loop Pipelining Method and Its Evaluation |
Yusuke Nakatsuji, Masahiro Nambu, Takashi Kambe (Kinki Univ.) |
(12) |
15:40-16:05 |
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(13) |
16:05-16:30 |
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