Wed, Dec 2 AM
10:20 - 11:40 |
(1)
ICD |
10:20-10:40 |
A Circuit Design Method based on Foreknown Regularity between I/O |
Jin Sato, Tsugio Nakamura, Hiroshi Kasahara, Narito Fuyutsume (Tokyo Denki Univ.) |
(2)
ICD |
10:40-11:00 |
Implementation of Asynchronous Bus for GALS System |
Takehiro Hori, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) |
(3)
ICD |
11:00-11:20 |
A WiMAX Turbo Decoder with Tailbiting BIP Architecture |
Hiroaki Arai, Naoto Miyamoto, Koji Kotani (Tohoku Univ.), Hisanori Fujisawa (Fujitsu Laboratories Ltd.), Takashi Ito (Tohoku Univ.) |
(4)
ICD |
11:20-11:40 |
A Reference CMOS Circuit Structure for Evaluation of Power Supply Noise |
Tetsuro Matsuno, Daisuke Kosaka (Kobe Univ.), Makoto Nagata (Kobe Univ./ CREST-JST) |
Wed, Dec 2 PM
13:15 - 17:00 |
| (5) |
13:15-13:50 |
[Invited Talk]
PI/SI/EMI for Chip/Package/Board Co-Design |
Hideki Asai (Shizuoka Univ.) |
| (6) |
13:50-14:25 |
[Invited Talk]
Failures due to Terrestriall Neutrons in Most Advanced Semicondutor Devices
-- Impacts and Hardening Techniques down to 22nm Design Rule -- |
Eishi Ibe, Kenichi Shimbo, Hitoshi Taniguchi, Tadanobu Toba (Hitachi, Ltd.) |
| (7) |
14:25-15:00 |
[Invited Talk]
Noise characteristics improvement of an LSI by using an interposer embedded capacitors |
Yoshiyuki Saito, Eiji Takahashi, Chie Sasaki (Panasonic), Yasuhiro Sugaya (Panasonic Electronic Devices) |
| |
15:00-15:15 |
Break ( 15 min. ) |
| (8) |
15:15-15:50 |
[Invited Talk]
EMC jisso Design at GHz frequencies |
Takashi Harada, Naoki Kobayashi, Ken Morishita, Hisashi Ishida (NEC Corp.) |
| |
15:50-16:00 |
Break ( 10 min. ) |
| (9) |
16:00-17:00 |
[Panel Discussion]
EMC Circuit Design and Jisso Design for System LSI
-- Proposal for Circuit Design Managing EMC and Jisso Issue from Jisso-side -- |
Hideki Osaka (HITACHI Ltd.), Hideki Asai (Shizuoka Univ.), Hidefumi Ibe (HITACHI Ltd.), Yoshiyuki Saito (Panasonic), Takashi Harada (NEC), Narimasa Takahashi (IBM Japan) |
Wed, Dec 2 PM
13:25 - 15:05 |
| (10) |
13:25-13:45 |
|
| (11) |
13:45-14:05 |
|
(12)
VLD |
14:05-14:25 |
Multiplexer Minimization Based on Complete ILP Description of High-Level Synthesis |
Keisuke Inoue (JAIST/JSPS), Mineo Kaneko (JAIST) |
(13)
VLD |
14:25-14:45 |
A Method to Reduce Power Dissipation of Conditional Operations with Execution Probabilities and its Application to Dual Supply Voltage System |
Kazuhito Ito, HyunJoon Kim (Saitama Univ.) |
(14)
VLD |
14:45-15:05 |
A Resource Binding Method to Reduce Data Communication Power Dissipation on LSI |
Hidekazu Seto, Kazuhito Ito (Saitama Univ.) |
| |
15:05-15:20 |
Break ( 15 min. ) |
Wed, Dec 2 PM
15:20 - 16:40 |
(15)
VLD |
15:20-15:40 |
Evaluation of Hardware/Software Partitioning Method with Consideration of Timing |
Junya Matsunaga, Michiaki Muraoka (Kochi Univ.) |
(16)
VLD |
15:40-16:00 |
Two-level Cache Simulation with L2 Unified Cache for Embedded Applications |
Yuta Kobayashi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) |
(17)
VLD |
16:00-16:20 |
Simulation-Based Bus Width Optimization for Two-Level Cache |
Shinta Watanabe, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) |
| (18) |
16:20-16:40 |
|
Thu, Dec 3 AM
10:00 - 11:35 |
(19)
CPM |
10:00-10:20 |
Correlation of Mitigation of Soft-error Rate of Routers between Neutron Irradiation Test and Field Soft-error Data |
Kenichi Shimbo, Tadanobu Toba, Hidehumi Ibe, Koji Nishii (Hitachi) |
(20)
CPM |
10:20-10:40 |
A Target Imedance of Power Distribution Network and LSI Packaging Design |
Narimasa Takahashi, Yoshiyuki Kosaka, Masatoshi Ishii (IBM Japan), Makoto Shiroshita (KYOCERA SLC) |
(21)
CPM |
10:40-11:00 |
Evaluation of Waveform-Improvement performance on the Segmental Transmission Line |
Yuki Shimauchi, Hiroshi Nakayama, Yoshiki Yamaguchi, Noriyuki Aibe (Tsukuba Univ.), Ikuo Yoshihara (Miyazaki Univ.), Moritoshi Yasunaga (Tsukuba Univ.) |
| (22) |
11:00-11:35 |
[Invited Talk]
Study on the Signal Integrity Design of a High-Speed LSI and a Printed Circuit Board |
Seiichi Saito, Keitaro Yamagishi (Mitsubishi Electric) |
Thu, Dec 3 AM
10:00 - 11:40 |
(23)
VLD |
10:00-10:20 |
An Evaluation of Approximate Methods for Soft Error Tolerance Evaluation of Sequential Circuits |
Yusuke Akamine, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.) |
(24)
DC |
10:20-10:40 |
BILBO register with Soft Error Detection Function |
Masahiro Sugasawa, Kazuteru Namba, Hideo Ito (Chiba Univ.) |
(25)
DC |
10:40-11:00 |
An Approach to Dependable Chip Multiprocessors with Process Pair and Swap Mechanism |
Tomohide Nagai, Masashi Imai, Takashi Nanya (Univ. of Tokyo) |
(26)
DC |
11:00-11:20 |
A Quantitative Evaluation of Security for Scan-based Side Channel Attack and Countermeasures |
Yuma Ito, Masayoshi Yoshimura, Hiroto Yasuura (Kyushu Univ) |
| (27) |
11:20-11:40 |
|
Thu, Dec 3 AM
10:20 - 11:40 |
(28)
CPSY |
10:20-10:40 |
An Efficient GPU Implementation Approach of Smith-Waterman Algorithm |
Keisuke Dohi (Nagasaki Univ.), Ling Cheng (Univ of Edinburgh), Tsuyoshi Hamada, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.), Khaled Benkrid (Univ of Edinburgh) |
(29)
CPSY |
10:40-11:00 |
Improvement and evaluation of mode switching approach for Variable Level Cache |
Nobuyuki Matsubara, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo (Mie Univ.) |
(30)
CPSY |
11:00-11:20 |
Fine-grain Mode Transition Controller based on Dynamic Memory Access Analyzing for Variable Stages Pipeline |
Kazumasa Nomura, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo (Mie Univ.) |
(31)
CPSY |
11:20-11:40 |
Proposal of Multi-Core Processor PALS to Realize Two-Path Limited Speculation Method |
Hiroyoshi Jutori, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) |
Thu, Dec 3 PM
13:25 - 14:25 |
(32)
DC |
13:25-13:45 |
Detection of Fault Candidate portions by DEF data Visualization |
Kazuaki Kishi, Masaru Sanada (Kochi Univ. of Tech.) |
(33)
DC |
13:45-14:05 |
A Yield Model with Testability and Repairability |
Yujiro Amano, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) |
(34)
DC |
14:05-14:25 |
Optimizing Don't-Care Bit Rate Derived from X-Identification for Reduction of Switching Activity |
Isao Beppu (Kyushu Institute of Tech), Kohei Miyase (Kyushu Institute of Tech/JST), Yuta Yamato (Kyushu Institute of Tech), Xiaoqing Wen, Seiji Kajihara (Kyushu Institute of Tech/JST) |
| |
14:25-15:20 |
Break ( 55 min. ) |
Thu, Dec 3 PM
15:20 - 16:20 |
(35)
VLD |
15:20-15:40 |
Influence analysis of a holographic memory window of a programmable optically reconfigurable gate array |
Shinya Kubota, Minoru Watanabe (Shizuoka Univ.) |
(36)
VLD |
15:40-16:00 |
A Compact Adaptive Slope Compensation Circuit for Current-Mode DC-DC Converter |
Kimio Shibata, Cong-Kha Pham (Univ. of Electro-Comm.) |
| (37) |
16:00-16:20 |
|
Thu, Dec 3 PM
13:25 - 15:05 |
(38)
RECONF |
13:25-13:45 |
A Case Study of Error Correction Technique for SRAM-based FPGA using the Partial Reconfiguration |
Noritaka Kai, Yoshiaki Tsutsumi, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
(39)
RECONF |
13:45-14:05 |
An inversion/non-inversion dynamic optical reconfiguration architecture using a MEMS |
Daisaku Seto, Minoru Watanabe (Shizuoka Univ.) |
(40)
RECONF |
14:05-14:25 |
Optical buffering technique under space radiation environment |
Mao Nakajima, Minoru Watanabe (Shizuoka Univ.) |
(41)
RECONF |
14:25-14:45 |
Evaluation of circuit proliferation method that uses concept of pressure in PCA |
Yuta Araki, Yuichiro Shibata, Tsuyoshi Hamada, Tomonari Masada, Kiyoshi Oguri (Nagasaki Univ.) |
(42)
RECONF |
14:45-15:05 |
Protocol for Expansion of Hardware in a Scalable FPGA System |
Hironori Nakajo, Ryuichi Sakamoto, Shinobu Miwa (TUAT) |
| |
15:05-15:20 |
Break ( 15 min. ) |
Thu, Dec 3 PM
15:20 - 16:20 |
(43)
RECONF |
15:20-15:40 |
A Virus Scanning Engine Using a Parallel Sieve Method and the MPU |
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.), Yoshifumi Kawamura (Renesas Technology Corp.) |
(44)
RECONF |
15:40-16:00 |
Development of Standard Evaluation Environment for Side-channel Attacks and Countermeasures |
Toshihiro Katashita (AIST), Yohei Hori (Chuo Univ.), Akashi Satoh (AIST) |
(45)
RECONF |
16:00-16:20 |
Evaluation of CryptMT steam cipher implemented on FPGA |
Naoko Yamada (Keio Univ.), Atsunori Sakurai, Keisuke Iwai, Takakazu Kurokawa (National Defense Academy), Hideharu Amano (Keio Univ.) |
Thu, Dec 3 PM
16:30 - 18:00 |
| (46) |
16:30-18:00 |
|
Fri, Dec 4 AM
10:00 - 11:40 |
(47)
VLD |
10:00-10:20 |
A Logic Simulation Method with Consideration of Delay Time Variation by Crosstalk |
Masayuki Kobayashi, Wataru Sento, Masahiko Toyonaga, Michiaki Muraoka (Kochi Univ.) |
(48)
VLD |
10:20-10:40 |
Increasing Yield Using Partially-Programmable Circuits |
Shigeru Yamashita (Ritsumeikan Univ.), Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo) |
(49)
VLD |
10:40-11:00 |
Transistor-Array-Based Opamp Layout and its Evaluationon |
Arisa Kawazoe, Toru Fujimura, Shigetoshi Nakatake (Univ. of Kitakyushu) |
(50)
VLD |
11:00-11:20 |
Analysis of Layout Structure Dependence on Distance/Space Variation for MOS Transistors |
Yuichi Sadohira, Shigetoshi Nakatake (Univ. of Kitakyusyu) |
| (51) |
11:20-11:40 |
|
Fri, Dec 4 AM
10:20 - 11:40 |
(52)
CPSY |
10:20-10:40 |
Precise Detection of Stack-Smashing Attacks and Requirements for its Efficient Implement |
Shohei Noma, Atsushi Nunome, Hiroaki Hirata, Kiyoshi Shibayama (Kyoto Inst. of Tech.) |
(53)
CPSY |
10:40-11:00 |
A Proposal of Message Driven IP Core Interface |
Ryuta Sasaki, Tsugio Nakamura, Hiroshi Kasahara, Narito Fuyutsume (Tokyo Denki Univ.) |
(54)
CPSY |
11:00-11:20 |
A Proposal of a Computer Architecture for Numbers of Arbitrary Word Length and its Implementation
-- On the Instruction Control Unit -- |
Yuta Totsuka, Masamichi Makino, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara (Tokyo Denki Univ.) |
(55)
CPSY |
11:20-11:40 |
A Proposal of a Computer Architecture for Numbers of Arbitrary Word Length and its Implementation
-- On the Memory Management Unit -- |
Masamichi Makino, Yuta Totsuka, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara (Tokyo Denki Univ.) |
Fri, Dec 4 AM
10:00 - 11:00 |
(56)
RECONF |
10:00-10:20 |
"FLOPS2D" Design Concept
-- Floating Point Custom Computer for CFD -- |
Naoyuki Fujita (JAXA) |
(57)
RECONF |
10:20-10:40 |
A Study of two input LUT array type programmable logic architecture for cryptographic processing |
Ai Nakanishi, Kouta Ishibashi, Yuuichirou Kurokawa, Takeshi Fujino (Ritsumeikan Univ.) |
(58)
RECONF |
10:40-11:00 |
Selection Technique of Pipeline Parameters for FLOPS-2D:Multi-FPGA System Environment |
Hirokazu Morishita, Kenta Inakagata (Keio Univ.), Yasunori Osana (Seikei Univ.), Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.) |
Fri, Dec 4 PM
13:25 - 14:45 |
(59)
DC |
13:25-13:45 |
A Test Compaction Oriented Don't Care Identification Method |
Motohiro Wakazono, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.) |
(60)
DC |
13:45-14:05 |
A secure design for testability of RSA Encryption circuits |
Teppei Hayakawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.) |
(61)
DC |
14:05-14:25 |
Logic stabilization way of open fault with unsuitable logic
-- Aim in simple diagnosis technology -- |
Masaru Sanada (Koch Univ. of Tech.), Keishi Hashida (Renesas Design), Taiki Yasutomi (Koch Univ. of Tech.) |
(62)
DC |
14:25-14:45 |
A Path Selection Method of Delay Test for Transistor Aging |
Mitsumasa Noda (Kyushu Institute of Tech.), Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen (Kyushu Institute of Tech./JST), Yukiya Miura (Tokyo Metropolitan Univ./JST) |
| |
14:45-15:00 |
Break ( 15 min. ) |
Fri, Dec 4 PM
15:00 - 16:20 |
(63)
VLD |
15:00-15:20 |
Evaluation of Energy Consumption on Multipliers Using the Sum of Operands |
Hirotaka Kawashima, Naofumi Takagi (Nagoya Univ.) |
(64)
VLD |
15:20-15:40 |
Automatic Generation of Design-Specific Cell Libraries |
Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo/JST) |
(65)
VLD |
15:40-16:00 |
FlexMerge: A Logic Optimization Technique to Minimize Area for LUT-based FPGAs |
Taiga Takata, Yusuke Matsunaga (Kyushu Univ.) |
| (66) |
16:00-16:20 |
|
Fri, Dec 4 PM
13:25 - 14:25 |
(67)
RECONF |
13:25-14:25 |
[Invited Talk]
A Project on Dynamically Reconfigurable Processors: MuCCRA
-- Design emvironment, Low Power design and 3D wireless interconnect -- |
Hideharu Amano (Keio Univ.) |
| |
14:25-15:00 |
Break ( 35 min. ) |
Fri, Dec 4 PM
15:00 - 16:00 |
(68)
RECONF |
15:00-15:20 |
An Optimal Algorithm for 3-adress QDD Machine Code |
Taisuke Fukuyama, Tsutomu Sasao, Munehiro Matsuura (Kyusyu Inst. of Tech.) |
(69)
RECONF |
15:20-15:40 |
Performance Evaluation of Dynamially Reconfigurable VLD Circuit |
Kiyotaka Komoku, Takashi Miyake, Takayuki Morishita (Okayama Pref. Univ.) |
(70)
RECONF |
15:40-16:00 |
Implementation of core functions of a H264 encoder on STP-engine |
Yoshihiro Takamatsu, Takao Toi, Hideharu Amano (Keio Univ.) |
: 
bu
-u
ulty
ba-u