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=============================================== Technical Committee on VLSI Design Technologies (VLD) Chair: Atsushi Takahashi (Osaka Univ.) Vice Chair: Ikuo Harada (NTT) Secretary: Nozomu Togawa (Waseda Univ.), Akihisa Yamada (Sharp) =============================================== Technical Committee on Component Parts and Materials (CPM) Chair: Kanji Yasui (Nagaoka Univ. of Tech.) Vice Chair: Yasushi Takemura (Yokohama National Univ.) Secretary: Naoki Oba (NTT), Satoru Noge (Numazu National College of Tech.) Assistant: Tadayuki Imai (NTT), Katsuya Abe (Shinshu Univ.) =============================================== Technical Committee on Integrated Circuits and Devices (ICD) Chair: Kunio Uchiyama (Hitachi) Vice Chair: Masahiko Yoshimoto (Kobe Univ.), Toshihiko Hamasaki (TI) Secretary: Minoru Fujishima (Univ. of Tokyo), Yoshio Hirose (Fujitsu Labs.) Assistant: Hiroaki Suzuki (Renesas), Toshimasa Matsuoka (Osaka Univ.), Kenichi Okada (Tokyo Inst. of Tech.) =============================================== Technical Committee on Computer Systems (CPSY) Chair: Shuichi Sakai (Univ. of Tokyo) Vice Chair: Yoshio Miki (Hitachi), Hideharu Amano (Keio Univ.) Secretary: Morihiro Kuga (Kumamoto Univ.), Hiroshi Ueno (NEC) Assistant: Hidetsugu Irie (Univ. of Tokyo) =============================================== Technical Committee on Dependable Computing (DC) Chair: Takashi Aikyo (STARC) Vice Chair: Tomohiro Yoneda (NII) Secretary: Masato Kitagami (Chiba Univ.), Michinobu Nakao (Renesas) =============================================== Technical Committee on Reconfigurable Systems (RECONF) Chair: Akira Nagoya (Okayama Univ.) Vice Chair: Tetsuo Hironaka (Hiroshima City Univ.), Shorin Kyo (NEC) Secretary: Tomonori Izumi (Ritsumeikan Univ.), Yohei Hori (Chuo Univ.) Assistant: Nobuya Watanabe (Okayama Univ.) =============================================== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) Chair: Shinji Kimura Secretary: Takashi Aoki, Naoyuki Hoshi, Kenshu Seto DATE: Wed, Dec 2, 2009 10:20 - 17:00 Thu, Dec 3, 2009 10:00 - 18:00 Fri, Dec 4, 2009 10:00 - 16:20 PLACE: Kochi City Culture Plaza(2-1 Kutanda, Kochi, 780-8529 Japan. http://www.bunkaplaza.or.jp/. Prof. Masayoshi Tachibana. +81-887-57-2212) TOPICS: Design Gaia 2009 ―New Field of VLSI Design― ---------------------------------------- Wed, Dec 2 AM (10:20 - 11:40) ---------------------------------------- (1)/ICD 10:20 - 10:40 A Circuit Design Method based on Foreknown Regularity between I/O Jin Sato, Tsugio Nakamura, Hiroshi Kasahara, Narito Fuyutsume (Tokyo Denki Univ.) (2)/ICD 10:40 - 11:00 Implementation of Asynchronous Bus for GALS System Takehiro Hori, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) (3)/ICD 11:00 - 11:20 A WiMAX Turbo Decoder with Tailbiting BIP Architecture Hiroaki Arai, Naoto Miyamoto, Koji Kotani (Tohoku Univ.), Hisanori Fujisawa (Fujitsu Laboratories Ltd.), Takashi Ito (Tohoku Univ.) (4)/ICD 11:20 - 11:40 A Reference CMOS Circuit Structure for Evaluation of Power Supply Noise Tetsuro Matsuno, Daisuke Kosaka (Kobe Univ.), Makoto Nagata (Kobe Univ./ CREST-JST) ---------------------------------------- Wed, Dec 2 PM (13:15 - 17:00) ---------------------------------------- (5) 13:15 - 13:50 [Invited Talk] PI/SI/EMI for Chip/Package/Board Co-Design Hideki Asai (Shizuoka Univ.) (6) 13:50 - 14:25 [Invited Talk] Failures due to Terrestriall Neutrons in Most Advanced Semicondutor Devices -- Impacts and Hardening Techniques down to 22nm Design Rule -- Eishi Ibe, Kenichi Shimbo, Hitoshi Taniguchi, Tadanobu Toba (Hitachi, Ltd.) (7) 14:25 - 15:00 [Invited Talk] Noise characteristics improvement of an LSI by using an interposer embedded capacitors Yoshiyuki Saito, Eiji Takahashi, Chie Sasaki (Panasonic), Yasuhiro Sugaya (Panasonic Electronic Devices) ----- Break ( 15 min. ) ----- (8) 15:15 - 15:50 [Invited Talk] EMC jisso Design at GHz frequencies Takashi Harada, Naoki Kobayashi, Ken Morishita, Hisashi Ishida (NEC Corp.) ----- Break ( 10 min. ) ----- (9) 16:00 - 17:00 [Panel Discussion] EMC Circuit Design and Jisso Design for System LSI -- Proposal for Circuit Design Managing EMC and Jisso Issue from Jisso-side -- Hideki Osaka (HITACHI Ltd.), Hideki Asai (Shizuoka Univ.), Hidefumi Ibe (HITACHI Ltd.), Yoshiyuki Saito (Panasonic), Takashi Harada (NEC), Narimasa Takahashi (IBM Japan) ---------------------------------------- Wed, Dec 2 PM (13:25 - 15:05) ---------------------------------------- (10) 13:25 - 13:45 (11) 13:45 - 14:05 (12)/VLD 14:05 - 14:25 Multiplexer Minimization Based on Complete ILP Description of High-Level Synthesis Keisuke Inoue (JAIST/JSPS), Mineo Kaneko (JAIST) (13)/VLD 14:25 - 14:45 A Method to Reduce Power Dissipation of Conditional Operations with Execution Probabilities and its Application to Dual Supply Voltage System Kazuhito Ito, HyunJoon Kim (Saitama Univ.) (14)/VLD 14:45 - 15:05 A Resource Binding Method to Reduce Data Communication Power Dissipation on LSI Hidekazu Seto, Kazuhito Ito (Saitama Univ.) ----- Break ( 15 min. ) ----- ---------------------------------------- Wed, Dec 2 PM (15:20 - 16:40) ---------------------------------------- (15)/VLD 15:20 - 15:40 Evaluation of Hardware/Software Partitioning Method with Consideration of Timing Junya Matsunaga, Michiaki Muraoka (Kochi Univ.) (16)/VLD 15:40 - 16:00 Two-level Cache Simulation with L2 Unified Cache for Embedded Applications Yuta Kobayashi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) (17)/VLD 16:00 - 16:20 Simulation-Based Bus Width Optimization for Two-Level Cache Shinta Watanabe, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) (18) 16:20 - 16:40 ---------------------------------------- Thu, Dec 3 AM (10:00 - 11:35) ---------------------------------------- (19)/CPM 10:00 - 10:20 Correlation of Mitigation of Soft-error Rate of Routers between Neutron Irradiation Test and Field Soft-error Data Kenichi Shimbo, Tadanobu Toba, Hidehumi Ibe, Koji Nishii (Hitachi) (20)/CPM 10:20 - 10:40 A Target Imedance of Power Distribution Network and LSI Packaging Design Narimasa Takahashi, Yoshiyuki Kosaka, Masatoshi Ishii (IBM Japan), Makoto Shiroshita (KYOCERA SLC) (21)/CPM 10:40 - 11:00 Evaluation of Waveform-Improvement performance on the Segmental Transmission Line Yuki Shimauchi, Hiroshi Nakayama, Yoshiki Yamaguchi, Noriyuki Aibe (Tsukuba Univ.), Ikuo Yoshihara (Miyazaki Univ.), Moritoshi Yasunaga (Tsukuba Univ.) (22) 11:00 - 11:35 [Invited Talk] Study on the Signal Integrity Design of a High-Speed LSI and a Printed Circuit Board Seiichi Saito, Keitaro Yamagishi (Mitsubishi Electric) ---------------------------------------- Thu, Dec 3 AM (10:00 - 11:40) ---------------------------------------- (23)/VLD 10:00 - 10:20 An Evaluation of Approximate Methods for Soft Error Tolerance Evaluation of Sequential Circuits Yusuke Akamine, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.) (24)/DC 10:20 - 10:40 BILBO register with Soft Error Detection Function Masahiro Sugasawa, Kazuteru Namba, Hideo Ito (Chiba Univ.) (25)/DC 10:40 - 11:00 An Approach to Dependable Chip Multiprocessors with Process Pair and Swap Mechanism Tomohide Nagai, Masashi Imai, Takashi Nanya (Univ. of Tokyo) (26)/DC 11:00 - 11:20 A Quantitative Evaluation of Security for Scan-based Side Channel Attack and Countermeasures Yuma Ito, Masayoshi Yoshimura, Hiroto Yasuura (Kyushu Univ) (27) 11:20 - 11:40 ---------------------------------------- Thu, Dec 3 AM (10:20 - 11:40) ---------------------------------------- (28)/CPSY 10:20 - 10:40 An Efficient GPU Implementation Approach of Smith-Waterman Algorithm Keisuke Dohi (Nagasaki Univ.), Ling Cheng (Univ of Edinburgh), Tsuyoshi Hamada, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.), Khaled Benkrid (Univ of Edinburgh) (29)/CPSY 10:40 - 11:00 Improvement and evaluation of mode switching approach for Variable Level Cache Nobuyuki Matsubara, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo (Mie Univ.) (30)/CPSY 11:00 - 11:20 Fine-grain Mode Transition Controller based on Dynamic Memory Access Analyzing for Variable Stages Pipeline Kazumasa Nomura, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo (Mie Univ.) (31)/CPSY 11:20 - 11:40 Proposal of Multi-Core Processor PALS to Realize Two-Path Limited Speculation Method Hiroyoshi Jutori, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) ---------------------------------------- Thu, Dec 3 PM (13:25 - 14:25) ---------------------------------------- (32)/DC 13:25 - 13:45 Detection of Fault Candidate portions by DEF data Visualization Kazuaki Kishi, Masaru Sanada (Kochi Univ. of Tech.) (33)/DC 13:45 - 14:05 A Yield Model with Testability and Repairability Yujiro Amano, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) (34)/DC 14:05 - 14:25 Optimizing Don't-Care Bit Rate Derived from X-Identification for Reduction of Switching Activity Isao Beppu (Kyushu Institute of Tech), Kohei Miyase (Kyushu Institute of Tech/JST), Yuta Yamato (Kyushu Institute of Tech), Xiaoqing Wen, Seiji Kajihara (Kyushu Institute of Tech/JST) ----- Break ( 55 min. ) ----- ---------------------------------------- Thu, Dec 3 PM (15:20 - 16:20) ---------------------------------------- (35)/VLD 15:20 - 15:40 Influence analysis of a holographic memory window of a programmable optically reconfigurable gate array Shinya Kubota, Minoru Watanabe (Shizuoka Univ.) (36)/VLD 15:40 - 16:00 A Compact Adaptive Slope Compensation Circuit for Current-Mode DC-DC Converter Kimio Shibata, Cong-Kha Pham (Univ. of Electro-Comm.) (37) 16:00 - 16:20 ---------------------------------------- Thu, Dec 3 PM (13:25 - 15:05) ---------------------------------------- (38)/RECONF 13:25 - 13:45 A Case Study of Error Correction Technique for SRAM-based FPGA using the Partial Reconfiguration Noritaka Kai, Yoshiaki Tsutsumi, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) (39)/RECONF 13:45 - 14:05 An inversion/non-inversion dynamic optical reconfiguration architecture using a MEMS Daisaku Seto, Minoru Watanabe (Shizuoka Univ.) (40)/RECONF 14:05 - 14:25 Optical buffering technique under space radiation environment Mao Nakajima, Minoru Watanabe (Shizuoka Univ.) (41)/RECONF 14:25 - 14:45 Evaluation of circuit proliferation method that uses concept of pressure in PCA Yuta Araki, Yuichiro Shibata, Tsuyoshi Hamada, Tomonari Masada, Kiyoshi Oguri (Nagasaki Univ.) (42)/RECONF 14:45 - 15:05 Protocol for Expansion of Hardware in a Scalable FPGA System Hironori Nakajo, Ryuichi Sakamoto, Shinobu Miwa (TUAT) ----- Break ( 15 min. ) ----- ---------------------------------------- Thu, Dec 3 PM (15:20 - 16:20) ---------------------------------------- (43)/RECONF 15:20 - 15:40 A Virus Scanning Engine Using a Parallel Sieve Method and the MPU Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.), Yoshifumi Kawamura (Renesas Technology Corp.) (44)/RECONF 15:40 - 16:00 Development of Standard Evaluation Environment for Side-channel Attacks and Countermeasures Toshihiro Katashita (AIST), Yohei Hori (Chuo Univ.), Akashi Satoh (AIST) (45)/RECONF 16:00 - 16:20 Evaluation of CryptMT steam cipher implemented on FPGA Naoko Yamada (Keio Univ.), Atsunori Sakurai, Keisuke Iwai, Takakazu Kurokawa (National Defense Academy), Hideharu Amano (Keio Univ.) ---------------------------------------- Thu, Dec 3 PM (16:30 - 18:00) ---------------------------------------- (46) 16:30 - 18:00 ---------------------------------------- Fri, Dec 4 AM (10:00 - 11:40) ---------------------------------------- (47)/VLD 10:00 - 10:20 A Logic Simulation Method with Consideration of Delay Time Variation by Crosstalk Masayuki Kobayashi, Wataru Sento, Masahiko Toyonaga, Michiaki Muraoka (Kochi Univ.) (48)/VLD 10:20 - 10:40 Increasing Yield Using Partially-Programmable Circuits Shigeru Yamashita (Ritsumeikan Univ.), Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo) (49)/VLD 10:40 - 11:00 Transistor-Array-Based Opamp Layout and its Evaluationon Arisa Kawazoe, Toru Fujimura, Shigetoshi Nakatake (Univ. of Kitakyushu) (50)/VLD 11:00 - 11:20 Analysis of Layout Structure Dependence on Distance/Space Variation for MOS Transistors Yuichi Sadohira, Shigetoshi Nakatake (Univ. of Kitakyusyu) (51) 11:20 - 11:40 ---------------------------------------- Fri, Dec 4 AM (10:20 - 11:40) ---------------------------------------- (52)/CPSY 10:20 - 10:40 Precise Detection of Stack-Smashing Attacks and Requirements for its Efficient Implement Shohei Noma, Atsushi Nunome, Hiroaki Hirata, Kiyoshi Shibayama (Kyoto Inst. of Tech.) (53)/CPSY 10:40 - 11:00 A Proposal of Message Driven IP Core Interface Ryuta Sasaki, Tsugio Nakamura, Hiroshi Kasahara, Narito Fuyutsume (Tokyo Denki Univ.) (54)/CPSY 11:00 - 11:20 A Proposal of a Computer Architecture for Numbers of Arbitrary Word Length and its Implementation -- On the Instruction Control Unit -- Yuta Totsuka, Masamichi Makino, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara (Tokyo Denki Univ.) (55)/CPSY 11:20 - 11:40 A Proposal of a Computer Architecture for Numbers of Arbitrary Word Length and its Implementation -- On the Memory Management Unit -- Masamichi Makino, Yuta Totsuka, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara (Tokyo Denki Univ.) ---------------------------------------- Fri, Dec 4 AM (10:00 - 11:00) ---------------------------------------- (56)/RECONF 10:00 - 10:20 "FLOPS2D" Design Concept -- Floating Point Custom Computer for CFD -- Naoyuki Fujita (JAXA) (57)/RECONF 10:20 - 10:40 A Study of two input LUT array type programmable logic architecture for cryptographic processing Ai Nakanishi, Kouta Ishibashi, Yuuichirou Kurokawa, Takeshi Fujino (Ritsumeikan Univ.) (58)/RECONF 10:40 - 11:00 Selection Technique of Pipeline Parameters for FLOPS-2D:Multi-FPGA System Environment Hirokazu Morishita, Kenta Inakagata (Keio Univ.), Yasunori Osana (Seikei Univ.), Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.) ---------------------------------------- Fri, Dec 4 PM (13:25 - 14:45) ---------------------------------------- (59)/DC 13:25 - 13:45 A Test Compaction Oriented Don't Care Identification Method Motohiro Wakazono, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.) (60)/DC 13:45 - 14:05 A secure design for testability of RSA Encryption circuits Teppei Hayakawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.) (61)/DC 14:05 - 14:25 Logic stabilization way of open fault with unsuitable logic -- Aim in simple diagnosis technology -- Masaru Sanada (Koch Univ. of Tech.), Keishi Hashida (Renesas Design), Taiki Yasutomi (Koch Univ. of Tech.) (62)/DC 14:25 - 14:45 A Path Selection Method of Delay Test for Transistor Aging Mitsumasa Noda (Kyushu Institute of Tech.), Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen (Kyushu Institute of Tech./JST), Yukiya Miura (Tokyo Metropolitan Univ./JST) ----- Break ( 15 min. ) ----- ---------------------------------------- Fri, Dec 4 PM (15:00 - 16:20) ---------------------------------------- (63)/VLD 15:00 - 15:20 Evaluation of Energy Consumption on Multipliers Using the Sum of Operands Hirotaka Kawashima, Naofumi Takagi (Nagoya Univ.) (64)/VLD 15:20 - 15:40 Automatic Generation of Design-Specific Cell Libraries Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo/JST) (65)/VLD 15:40 - 16:00 FlexMerge: A Logic Optimization Technique to Minimize Area for LUT-based FPGAs Taiga Takata, Yusuke Matsunaga (Kyushu Univ.) (66) 16:00 - 16:20 ---------------------------------------- Fri, Dec 4 PM (13:25 - 14:25) ---------------------------------------- (67)/RECONF 13:25 - 14:25 [Invited Talk] A Project on Dynamically Reconfigurable Processors: MuCCRA -- Design emvironment, Low Power design and 3D wireless interconnect -- Hideharu Amano (Keio Univ.) ----- Break ( 35 min. ) ----- ---------------------------------------- Fri, Dec 4 PM (15:00 - 16:00) ---------------------------------------- (68)/RECONF 15:00 - 15:20 An Optimal Algorithm for 3-adress QDD Machine Code Taisuke Fukuyama, Tsutomu Sasao, Munehiro Matsuura (Kyusyu Inst. of Tech.) (69)/RECONF 15:20 - 15:40 Performance Evaluation of Dynamially Reconfigurable VLD Circuit Kiyotaka Komoku, Takashi Miyake, Takayuki Morishita (Okayama Pref. Univ.) (70)/RECONF 15:40 - 16:00 Implementation of core functions of a H264 encoder on STP-engine Yoshihiro Takamatsu, Takao Toi, Hideharu Amano (Keio Univ.) # CONFERENCE ANNOUNCEMENT: - We will have a banquet on Dec 3 (Thu). See http://www.ieice.org/~vld/2009/GaiaBanquet09.html in detail. === Technical Committee on VLSI Design Technologies (VLD) === # FUTURE SCHEDULE: Tue, Jan 26, 2010 - Wed, Jan 27, 2010: Keio Univ (Hiyoshi Campus) [Fri, Nov 13], Topics: FPGA Applications, etc Wed, Mar 10, 2010 - Fri, Mar 12, 2010: [Wed, Jan 20], Topics: Design Technology for System-on-Silicon # SECRETARY: Nozomu Togawa (Waseda Univ.) E-mail: n         Tel: +81-3-5286-3908, Fax: +81-3-3208-7439 # ANNOUNCEMENT: # See also VLD's homepage: http://www.ieice.org/~vld/ === Technical Committee on Component Parts and Materials (CPM) === # FUTURE SCHEDULE: Mon, Feb 1, 2010: [Mon, Nov 16] === Technical Committee on Integrated Circuits and Devices (ICD) === # FUTURE SCHEDULE: Mon, Dec 14, 2009 - Tue, Dec 15, 2009: Shizuoka University (Hamamatsu) [Tue, Oct 20] Thu, Jan 28, 2010 - Fri, Jan 29, 2010: T.B.D. [Tue, Nov 17] Mon, Mar 1, 2010: Kyushu Univ. [Mon, Feb 1], Topics: Technical Meeting on Silicon Analog RF Technologies # SECRETARY: Minoru Fujishima (The University of Tokyo) TEL 03-5841-7425,FAX 03-5841-8575 E-mail:   eetu-  === Technical Committee on Computer Systems (CPSY) === # FUTURE SCHEDULE: Tue, Jan 26, 2010 - Wed, Jan 27, 2010: Keio Univ (Hiyoshi Campus) [Fri, Nov 13], Topics: FPGA Applications, etc Fri, Mar 26, 2010 - Sun, Mar 28, 2010: [Fri, Jan 22] # SECRETARY: Morihiro KUGA (Kumamoto Univ.) TEL +81-96-342-3647, FAX +81-96-342-3599 E-mail:   am -u=== Technical Committee on Dependable Computing (DC) === # FUTURE SCHEDULE: Fri, Dec 11, 2009: [Tue, Oct 20] Mon, Feb 15, 2010: Kikai-Shinko-Kaikan Bldg. [Fri, Dec 11] Fri, Mar 26, 2010 - Sun, Mar 28, 2010: [Fri, Jan 22] # SECRETARY: Masato Kitakami Graduate School of Advanced Integration Science, Chiba University 1-33 Yayoi-cho Inage-ku, Chiba 263-8522 JAPAN TEL/FAX +43.290.3039 E-mail:    f ulty ba-u=== Technical Committee on Reconfigurable Systems (RECONF) === # FUTURE SCHEDULE: Tue, Jan 26, 2010 - Wed, Jan 27, 2010: Keio Univ (Hiyoshi Campus) [Fri, Nov 13], Topics: FPGA Applications, etc # SECRETARY: Nobuya WATANABE (Okayama Univ.) E-mail:  bu   -uTEL: +81-86-251-8251 FAX: +81-86-251-8251 === Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) === # FUTURE SCHEDULE: Tue, Jan 26, 2010 - Wed, Jan 27, 2010: Keio Univ (Hiyoshi Campus) [Fri, Nov 13], Topics: FPGA Applications, etc Fri, Mar 26, 2010 - Sun, Mar 28, 2010: [Fri, Jan 22] Last modified: 2009-11-26 12:08:32 |
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