Mon, Nov 28 AM
Chair: Kazuya Masu (Tokyo Inst. of Tech.)
10:00 - 11:40 |
(1)
CPM |
10:00-10:50 |
[Invited Talk]
The Past, Present, and Future of MEMS/CMOS Integration Technologies
-- Transitions in Device Processes and Design Techniques -- |
Hidekuni Takao (Kagawa Univ.) |
(2)
CPM |
10:50-11:40 |
[Invited Talk]
Microjoining Technology for Semiconductor Heterogeneoous Integration |
Tanemasa Asano (Kyushu Univ.) |
Mon, Nov 28 AM
Chair: Hiroshi Saito (Univ. of Aizu)
09:00 - 10:15 |
(3)
VLD |
09:00-09:25 |
The RG-DTM PUF utilizing the Time to Digital Converter |
Takahiko Murayama, Mitsuru Shiozaki, Kota Furuhashi, Takeshi Fujino (Ritsumeikan Univ.) |
(4)
VLD |
09:25-09:50 |
Scan-based Attack against Triple DES Cryptosystems Using Scan Signatures |
Hirokazu Kodera, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) |
(5)
VLD |
09:50-10:15 |
On Secure and Testable Scan Design Utilizing Shift Register Quasi-Equivalents |
Katsuya Fujiwara (Akita Univ.), Hideo Fujiwara (Osaka Gakuin Univ.), Hideo Tamamoto (Akita Univ.) |
Mon, Nov 28 AM
Chair: Taiki Amagasaki (Kumamoto Univ.)
10:30 - 11:45 |
(6)
VLD |
10:30-10:55 |
Degradation of Oscillation Frequency of Ring Oscillators Placed on a 90 nm FPGA |
Shouhei Ishii, Kazutoshi Kobayashi (KIT) |
(7)
VLD |
10:55-11:20 |
High accuracy of system LSI energy estimation |
Wang Xiang (Kyushu Univ.), Norifumi Yoshimatsu (ISIT), Kazuaki Murakami (Kyushu Univ.) |
(8)
VLD |
11:20-11:45 |
An Interrupt Service Handler in Hardware for Ultra-Low Latency Response |
Naotaka Maruyama (Kernelon Silicon), Tohru Ishihara (Kyoto Univ.), Hiroaki Takada (Nagoya Univ.), Hiroto Yasuura (Kyushu Univ.) |
Mon, Nov 28 PM
Chair: Hideharu Amano (Keio Univ.)
13:20 - 15:20 |
| (9) |
13:20-15:20 |
|
Mon, Nov 28 PM
Chair: Yoshiki Yamaguchi (Univ. of Tsukuba)
15:40 - 16:55 |
(10)
RECONF |
15:40-16:05 |
On a Power-Delay Product for a Heterogeneous MDD for ECFN Machine |
Hiroki Nakahara (Kagoshima Univ.), Tsutomu Sasao, Munehiro Matsuura (KIT) |
(11)
RECONF |
16:05-16:30 |
Fast soft-error recovery method for duplicated softcore processor system |
Yoshihiro Ichinomiya, Makoto Fujino, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) |
(12)
RECONF |
16:30-16:55 |
A configuration speed adjustment method on ORGAs |
Takashi Yoza, Minoru Watanabe (Shizuoka Univ.) |
Mon, Nov 28 PM
Chair: Kazuya Masu (Tokyo Inst. of Tech.)
13:00 - 15:30 |
(13)
CPM |
13:00-13:50 |
[Invited Talk]
MEMS Microwave Tunable Filters on High-K LTCC
-- Featuring Low Insertion Loss and Small Sized -- |
Fumihiko Nakazawa, Xiaoyu Mi, Osamu Toyoda, Satoshi Ueda (Fujitsu Lab.) |
(14)
CPM |
13:50-14:40 |
[Invited Talk]
An RF-MEMS tunable capacitor with CMOS driver IC |
Yoshiaki Sugizaki, Tamio Ikehashi, Hiroaki Yamazaki, Tomohiro Saito, Etsuji Ogawa, Yoshiaki Shimooka, Hideki Shibata (Toshiba) |
(15)
CPM |
14:40-15:05 |
Waveform-Improvement of High-speed Signals on Branch Traces on PCBs |
Yusuke Kuribara, Shohei Akita, Hiroki Shimada, Takuya Adachi, Hidetoshi Ishijima (Univ. Tsukuba), Ikuo Yoshihara (Univ. Miyazaki), Moritoshi Yasunaga (Univ. Tsukuba) |
(16)
CPM |
15:05-15:30 |
Towards an efficient simulation of SystemC Transaction Level Models |
Jun Furukawa (Kyushu Univ.), Norifumi Yoshimatsu (ISIT), Kazuaki Murakami (Kyushu Univ.) |
Mon, Nov 28 PM
15:30 - 17:00 |
| (17) |
15:30-17:00 |
Panel Discussion |
Mon, Nov 28 PM
Chair: Kazuki Namba (Chiba Univ.)
13:00 - 14:15 |
(18)
DC |
13:00-13:25 |
Fault-Detectable 2-Color Code for Asynchronous Bidirectional Communication Links |
Atsushi Matsumoto (Tohoku Univ.), Naoya Onizawa (McGill Univ.), Takahiro Hanyu (Tohoku Univ.) |
(19)
VLD |
13:25-13:50 |
Performance Evaluation of Soft-Error Tolerant Multiple Modular Processors Implemented with Redundant and Non-Redundant Flip-Flops |
Shogo Okada, Masaki Masuda (KIT), Jun Yao, Hajime Shimada (NAIST), Kazutoshi Kobayashi (KIT) |
(20)
DC |
13:50-14:15 |
A Dynamically Configurable NoC Test Access Mechanism |
Takieddine Sbiai, Kazuteru Namba, Hideo Ito (Chiba Univ.) |
Mon, Nov 28 PM
Chair: Yukihide Kohira (Univ. of Aizu)
14:20 - 15:35 |
(21)
VLD |
14:20-14:45 |
A Consideration on Wire-Sizing of Input Signals for System on Glass Liquid Crystal Display |
Taichi Suizu, Shuji Tsukiyama (Chuo Univ.) |
(22)
VLD |
14:45-15:10 |
Analytical Placement for Convex Blocks |
Tomoaki Gotanda, Masatomo Kuwano, Yasuhiro Takashima (Univ. of Kitakyushu) |
(23)
VLD |
15:10-15:35 |
An Acceleration Method for Power Grid Analysis using Block-Iterative Algorithm |
Takumi Morishita, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato (Kyoto Univ.) |
Mon, Nov 28 PM
Chair: Kenshu Seto (Tokyo Metro. Univ.)
15:40 - 16:55 |
(24)
VLD |
15:40-16:05 |
A Fast Transient Analysis of Linear Circuit using Quasi Zero Variance Importance Sampling |
Tetsuro Miyakawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato (Kyoto Univ.) |
(25)
VLD |
16:05-16:30 |
CMOS Op-amp Offset Calibration Technique Using a Closed Loop Offset Amplifier and Compact Resistor String DAC |
Hiroyuki Morimoto, Hiroaki Goto (KIT), Hajime Fujiwara (NJR), Kazuyuki Nakamura (KIT) |
(26)
VLD |
16:30-16:55 |
A study on parameter estimation for modeling of random-telegraph noise |
Hiromitsu Awano, Hirofumi Shimizu, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato (Kyoto Univ.) |
Tue, Nov 29 AM
Chair: Hiroaki Yoshida (Univ. of Tokyo)
09:00 - 10:40 |
(27)
VLD |
09:00-09:25 |
Synthesis of efficient data fetch mechanism from the high level communication description |
Masato Minato, Yuki Ando, Seiya Shibata (Nagoya Univ.), Tomoo Kinoshita (Soliton Systems), Shinya Honda, Hiroaki Takada (Nagoya Univ.) |
(28)
VLD |
09:25-09:50 |
A Runtime Mechanism for Managing of the Scratch-Pad Memory within Real-Time Operating Systems |
Hideki Takase, Hiroaki Takada (Nagoya Univ.) |
(29)
VLD |
09:50-10:15 |
Automatic Loop Fusion for High Level Synthesis using Outer Loop Shifting |
Yuta Kato, Kenshu Seto, Takuya Maruizumi (TCU) |
(30)
VLD |
10:15-10:40 |
A Hardware/Software Co-Design Method Optimized for High-Level Synthesis
-- Application to Android Platforms -- |
Hitoki Ito, Kiyofumi Tanaka (JAIST) |
Tue, Nov 29 AM
Chair: Hiroshi Yamada (Toshiba)
09:00 - 10:40 |
(31)
CPM |
09:00-09:50 |
[Invited Talk]
A new data format for designing device embedded substrates |
Hajime Tomokage (Fukuoka Univ.), Hidemichi Kawase (Keirex Tech.) |
(32)
CPM |
09:50-10:40 |
[Invited Talk]
High-Density Wiring Technology for LSI Packages |
Motoaki Tani, Shinya Sasaki (FUJITSU LAB.), Keisuke Uenishi (Osaka Univ.) |
Tue, Nov 29 AM
Chair: Seiya Watanabe (Okayama Univ.)
09:00 - 10:40 |
(33)
RECONF |
09:00-09:25 |
Implementation of the DTMF Signal Eliminate System by FPGA |
Takuya Goto, Hao San, Masao Hotta (TCU), Yoshihiro Baba, Hirokatsu Saito, Toshiaki Koyahara (NAKAYO) |
(34)
RECONF |
09:25-09:50 |
Evaluation of Out-Of-Order System for FaSTAR Implemented on FPGAs |
Takayuki Akamine, Kenta Inakagata (Keio Univ.), Yasunori Osana (Ryukyu Univ.), Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.) |
(35)
RECONF |
09:50-10:15 |
A good similarity of a datapath classification method for FPGA-based accelerator systems |
Yui Ogawa (Nagasaki Univ.), Yasunori Osana (Ryukyu Univ.), Masato Yoshimi (Doshisha Univ.), Akira Funahashi, Noriko Hiroi, Hideharu Amano (Keio Univ.), Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) |
(36)
RECONF |
10:15-10:40 |
CP-SAR Image Processing System Using Two FPGA Board and PC in UAV |
Koshi Oishi, Kazuteru Namba, Hideo Ito, Josaphat Tetuko Sri Sumantyo (Chiba Univ.) |
Tue, Nov 29 AM
Chair: Kohei Miayase
09:00 - 10:40 |
(37)
DC |
09:00-09:25 |
Modeling Economics of LSI Design and Manufacturing for Selecting Test Design. |
Noboru Shimizu, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) |
(38)
DC |
09:25-09:50 |
Improvement of Test Data Compression Rate for Chiba-Scan Testing by Reconstructing Scan Chain |
Masato Akagawa, Kazuteru Namba, Hideo Ito (Chiba univ.) |
(39)
DC |
09:50-10:15 |
A Scan Chain Construction Method to Reduce Test Data Volume on BAST |
Yun Chen, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.) |
(40)
DC |
10:15-10:40 |
A BIST-Aided Scan Test using Shifting Inverter Code and a TPG Method for Test Data Reduction |
Yasuhiko Okada, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima) |
Tue, Nov 29 AM
Chair: Hideharu Amano (Keio Univ.)
11:00 - 11:50 |
| (41) |
11:00-11:50 |
[Fellow Memorial Lecture]
Safe, Secure and Reliable Society by Electronics and InformationTechnology
-- What and how should we protect? -- |
Shuichi Sakai (UT) |
Tue, Nov 29 PM
Chair: Sumio Morioka (NEC)
13:00 - 15:05 |
(42)
CPSY |
13:00-13:25 |
A Study of Employing Java as A High-level Synthesis Language for FPGA |
Takefumi Miyoshi (UEC), Satoshi Funada (e-trees) |
(43)
CPSY |
13:25-13:50 |
A Scaling Method for a Large FU Array Accerlator on Multiple FPGAs |
Kodai Moritaka, Shunsuke Shitaoka, Kazuhiro Yoshimura, Jun Yao, Takashi Nakada, Yasuhiko Nakashima (NAIST) |
(44)
CPSY |
13:50-14:15 |
Power Estimation of Variable Stages Pipeline Processor Using Power Gating Technique |
Masaki Tanaka, Takahiro Sasaki, Tomoyuki Nakabayashi, Kazuhiko Ohno, Toshio Kondo (Mie Univ) |
(45)
CPSY |
14:15-14:40 |
A Study on Hardware Trojyan embedded Manchurian LSI for Cipher processing |
Takeshi Kumaki, Youhei Mochizuki, Takeshi Fujino (Ritsumeikan Univ.) |
(46)
CPSY |
14:40-15:05 |
Platform for Tool as a Service
-- To serve development tools via cloud service -- |
Takayuki Kando (QTS), Tomohiro Moriyama, Norifumi Yoshimatsu (ISIT), Kazuaki Murakami (Kyushu Univ.) |
Tue, Nov 29 PM
Chair: Akira Onozawa (NTT)
13:00 - 15:05 |
(47)
VLD |
13:00-13:25 |
Layout Methodology for Self-Alinged Double Patterning |
Chikaaki Kodama, Koichi Nakayama, Toshiya Kotani, Shigeki Nojima, Shoji Mimotogi, Shinji Miyamoto (Toshiba) |
(48)
VLD |
13:25-13:50 |
An Integer Linear Programming based Multiple Task Allocation Method for Fault Tolerance in Network on Chip |
Hiroshi Saito (Univ. Aizu), Tomohiro Yoneda (NII), Yuichi Nakamura (NEC) |
(49)
VLD |
13:50-14:15 |
Ymtools: an infrastructure for research and development of logic synthesis and verification |
Yusuke Matsunaga (Kyushu Univ.) |
(50)
VLD |
14:15-14:40 |
A Basic Study on Timing-Test Scheduling for Post-Silicon Skew Tuning |
Mineo Kaneko (JAIST) |
(51)
VLD |
14:40-15:05 |
A Hardware Development by C Source Code Visualization |
Akitoshi Matsuda, Shinichi Baba, Hirofumi Takamoto (Q's Forum) |
Tue, Nov 29 PM
Chair: Masahiko Yoshimoto (Kobe Univ.)
13:00 - 15:30 |
(52)
CPM |
13:00-13:50 |
[Invited Talk]
Ultra-precision measurement & fabrication technology of LSI and its materials for the next generation.
-- Toward the atomic scale production applying novel opto-machanical methods -- |
Hiroshi Kubota, Yuki Soh, Seiya Matsukawa (Kumamoto Univ.), Kouji Kosaka, Tadayuki Kyotani (PMT) |
(53)
CPM |
13:50-14:40 |
[Invited Talk]
Integrated CMOS-MEMS Technology and Its Applications |
Hiroki Morimura, Toshishige Shimamura, Kei Kuwabara, Kazuyoshi Ono (NTT), Katsuyuki Machida (NTT-AT) |
(54)
ICD |
14:40-15:05 |
Implementation of an FU Array Accelerator and its Analysis |
Mitsutoshi Saito, Shunsuke Shitaoka, Kazuhiro Yoshimura, Jun Yao, Takashi Nakada, Yasuhiko Nakashima (NAIST) |
(55)
ICD |
15:05-15:30 |
Multi-core LSI Lifetime Extension by NBTI-Recovery-based Self-healing |
Takashi Matsumoto, Hiroaki Makino (Kyoto Univ.), Kazutoshi Kobayashi (Kyoto Inst. Tech.), Hidetoshi Onodera (Kyoto Univ.) |
Tue, Nov 29 PM
15:30 - 16:50 |
| (56) |
15:30-16:50 |
|
Tue, Nov 29
Chair: Kimiyoshi Usami(Shibaura Inst. of Tech.)
17:00 - 18:00 |
| (57) |
17:00-18:00 |
[Keynote Address]
Lithography : past, present, and future |
Shigeki Nojima (Toshiba) |
Wed, Nov 30 AM
Chair: Kimiyoshi Usami(Shibaura Inst. of Tech.)
09:00 - 09:50 |
(58)
VLD |
09:00-09:50 |
[Invited Talk]
Ultra Low Voltage Subthreshold Circuit Design |
Masanori Hashimoto (Osaka Univ.) |
Wed, Nov 30 AM
Chair: Tsuyoshi Iwagaki
10:05 - 11:45 |
(59)
DC |
10:05-10:30 |
Capture power reduction in multi-cycle test structure |
Hisato Yamaguchi, Makoto Matsuzono, Kohei Miyase, Yasuo Sato, Seiji Kajihara (KIT) |
(60)
DC |
10:30-10:55 |
On the design for testability method using Time to Digital Converter for detecting delay faults |
Hiroyuki Makimoto, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima) |
(61)
DC |
10:55-11:20 |
A study on path selection results of an adaptive field test with process variation and aging degradation for VLSI |
Satoshi Kashiwazaki, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyu Univ) |
(62)
DC |
11:20-11:45 |
A Method of Thermal Uniformity Control During BIST |
Eri Murata (NAIST), Satoshi Ohtake (Oita Univ.), Yasuhiko Nakashima (NAIST) |
Wed, Nov 30 AM
Chair: Satoshi Komatsu (Univ. of Tokyo)
10:05 - 11:45 |
(63)
VLD |
10:05-10:30 |
A length difference reduction algorithm by using flow in set pair routing problem for single layer PCB routing |
Yusaku Yamamoto, Atsushi Takahashi (Osaka Univ.) |
(64)
VLD |
10:30-10:55 |
An Improved Simulated Annealing for 3D Packing with Sequence Triple and Quintuple Representations |
Yiqiang Sheng (Tokyo Inst. of Tech.), Atsushi Takahashi (Osaka Univ.), Shuichi Ueno (Tokyo Inst. of Tech.) |
(65)
DC |
10:55-11:20 |
Controller-Sharing Based Asynchronous Power-Gating Scheme and Its Application |
Takao Kawano (Tohoku Univ.), Naoya Onizawa (McGill Univ.), Atsushi Matsumoto, Takahiro Hanyu (Tohoku Univ.) |
(66)
VLD |
11:20-11:45 |
Power-Gating Circuit Scheme for Transient-Glitch Energy Reduction |
Yuya Ohta, Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.) |
Wed, Nov 30 AM
Chair: Takefumi Miyoshi
09:00 - 11:20 |
(67)
CPSY |
09:00-09:25 |
An Acceleration Method for Three-Dimensional Smith-Waterman Algorithm on a GPU |
Saori Sudo, Masato Yoshimi, Mitsunori Miki (Doshisha Univ.) |
(68)
CPSY |
09:25-09:50 |
A Priority-Aware On-Chip Network Router for Reducing Priority Inversions |
Yujiro Sasagawa, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.) |
| |
09:50-10:05 |
Break ( 15 min. ) |
(69)
CPSY |
10:05-10:30 |
A DMR based Parmanent Error Locating Method for a Dependable FU Array |
Yohei Hazama, Jun Yao, Takashi Nakada, Yasuhiko Nakashima (NAIST) |
(70)
CPSY |
10:30-10:55 |
A Trial on formalization locality of reference, based on the reference density function |
Hiroshi Fukuchi (Kyushu Univ.), Takayuki Kando (QTS), Kazuaki Murakami (Kyushu Univ.) |
(71)
CPSY |
10:55-11:20 |
Inhibiting Fluctuation of Execution Time of Real Time Tasks using Tightly Coupled Memory |
Tomoaki Ukezono, Yuanzhe LIU, Kiyofumi Tanaka (JAIST) |
Wed, Nov 30 AM
Chair: Takeshi Yamamura (Fujitsu Lab.)
09:00 - 11:45 |
(72)
ICD |
09:00-09:25 |
A Circuit Partitioning Strategy for 3-D Integrated Floating-point Multipliers |
Kazushige Kawai, Jubee Tada (Yamagata Univ.), Ryusuke Egawa, Hiroaki Kobayashi (Tohoku Univ.), Gensuke Goto (Yamagata Univ.) |
(73)
ICD |
09:25-09:50 |
Measurements and Co-Simulation of On-Chip and On-Boad AC Power Noise in Digital Integrated Circuits |
Kumpei Yoshikawa, Yuta Sasaki (Kobe Univ.), Kouji Ichikawa (DENSO), Yoshiyuki Saito (Panasonic), Makoto Nagata (Kobe Univ./CREST,JST) |
| |
09:50-10:05 |
Break ( 15 min. ) |
(74)
ICD |
10:05-10:30 |
A 40nm 144mW VLSI Processor for Realtime 60k Word Continuous Speech Reconginion |
Takanobu Sugahara, Guangji He, Tsuyoshi Fujinaga, Yuki Miyamoto, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) |
(75)
ICD |
10:30-10:55 |
Immunity Evaluation of SRAM Core Using DPI with On-Chip Diagnosis Structures |
Takuya Sawada, Taku Toshikawa, Kumpei Yoshikawa (Kobe Univ.), Hidehiro Takata, Koji Nii (Renesas Electronics Corp.), Makoto Nagata (Kobe Univ.) |
(76)
ICD |
10:55-11:20 |
A 22-Gb/s and over-33-mega-frame/s throughput bridge-function unit in a low-latency OLT LSI for the coexistence of 10G-EPON and GE-PON |
Shoko Ohteru, Tomoaki Kawamura, Hiroki Suto, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata (NTT) |
(77)
ICD |
11:20-11:45 |
10G-EPON OLT and ONU LSIs for next-generation FTTx system |
Tomoaki Kawamura, Shoko Ohteru, Sadayuki Yasuda, Akihiko Miyazaki, Kenji Kawai, Ritsu Kusaba, Mamoru Nakanishi, Masami Urano, Tsugumichi Shibata (NTT) |
: 
ba
t
ulty
ba-u
bu
