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=============================================== Technical Committee on Computer Systems (CPSY) Chair: Toshinori Sueyoshi (Kumamoto Univ.) Vice Chair: Syuuichi Sakai (Univ. of Tokyo), Yoshio Miki (Hitachi) Secretary: Morihiro Kuga (Kumamoto Univ.), Akira Asato (Fujitsu Labs.) Assistant: Hidetsugu Irie (Univ. of Tokyo) =============================================== Technical Committee on VLSI Design Technologies (VLD) Chair: Nagisa Ishiura (Kwansei Gakuin Univ.) Vice Chair: Kazutoshi Wakabayashi (NEC) Secretary: Hiroyuki Ochi (Kyoto Univ.), Ichiro Kohno (Renesas) =============================================== Technical Committee on Reconfigurable Systems (RECONF) Chair: Hideharu Amano (Keio Univ.) Vice Chair: Nobuki Kajihara (NEC), Akira Nagoya (Okayama Univ.) Secretary: Masahiro Iida (Kumamoto Univ.), Tomonori Izumi (Ritsumeikan Univ.) Assistant: Yohei Hori (AIST) =============================================== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) Chair: Hidetoshi Onodera Secretary: Isaro Utsumi, Yutaka Tamiya, Tohru Ishihara DATE: Wed, Jan 16, 2008 10:15 - 18:15 Thu, Jan 17, 2008 08:40 - 18:05 PLACE: (http://www.keio.ac.jp/english/about_keio/campus_info/hiyoshi2.html) TOPICS: FPGA Applications, etc ---------------------------------------- Wed, Jan 16 AM (10:15 - 11:05) ---------------------------------------- (1) 10:15 - 11:05 [Invited Talk] Flex Power FPGA Hanpei Koike (AIST) ----- Lunch ( 60 min. ) ----- ---------------------------------------- Wed, Jan 16 PM (12:55 - 14:35) ---------------------------------------- (2) 12:55 - 13:20 High speed control system using Multilevel control circuit Hiroaki Maekawa, Ryuichi Tanaka, Masatoshi Sekine (TUAT) (3) 13:20 - 13:45 Scalable RHPC(Reconfigurable HPC) by using FPGA array Hiroaki Iijima, Kazuki Sato, Masatoshi Sekine (Tokyo Univ. of Agriculture and Technology) (4) 13:45 - 14:10 Evaluation of the Small-World Network Routing Structure for Cluster Based FPGAs Yuzo Nishioka, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) (5) 14:10 - 14:35 An optimization method of DMA transfer for the SRC-6 reconfigurable machine Sayaka Shida, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) ----- Break ( 10 min. ) ----- ---------------------------------------- Wed, Jan 16 PM (14:45 - 16:25) ---------------------------------------- (6) 14:45 - 15:10 A study of the effectiveness of dynamic partial reconfiguration for size and power reduction Yohei Hori, Hirofumi Sakane, Kenji Toda (AIST) (7) 15:10 - 15:35 Development of verification and power estimation methodology for circuits with Run Time Power Gating Mitsutaka Nakata, Toshiaki Shirai, Toshihiro Kashima, Seidai Takeda, Kimiyoshi Usami (S.I.T.), Naomi Seki, Yohei Hasegawa, Hideharu Amano (Keio Univ.) (8) 15:35 - 16:00 Physical design and Evaluation of MIPS R3000 processor applying Run Time Power Gating Toshiaki Shirai, Toshihiro Kashima, Seidai Takeda, Mitsutaka Nakata, Kimiyoshi Usami (S.I.T.), Yohei Hasegawa, Naomi Seki, Hideharu Amano (Keio Univ.) (9) 16:00 - 16:25 An efficient algorithm for RTL power macro modeling and library building Masaaki Ohtsuki, Masato Kawai, Tatsuya Koyagi, Masahiro Fukui (Ritsumeikan Univ.) ----- Break ( 10 min. ) ----- ---------------------------------------- Wed, Jan 16 PM (16:35 - 18:15) ---------------------------------------- (10) 16:35 - 17:00 Solving the Quadratic Assignment Problem by Hardware Based on a Systolic Algorithm Yoshihiro Kimura, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ.) (11) 17:00 - 17:25 A Regular Expression String Matching Machine Allowing Pattern Setting During Execution Time and Its FPGA Implementation Yosuke Kawanaka, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ.) (12) 17:25 - 17:50 Fast solution method of Set Cover Problem on parallel reconfigurable processor DAPDNA-2 Hiroyuki Ishikawa, Sho Shimizu, Yutaka Arakawa, Naoaki Yamanaka (Keio Univ.), Kosuke Shiba (IPFlex) (13) 17:50 - 18:15 A Method of Design and Update for an Address Generator Using a Hybrid Method Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (K.I.T.) ---------------------------------------- Thu, Jan 17 AM (08:40 - 10:05) ---------------------------------------- (14) 08:40 - 09:15 [Invited Talk] ICCAD summary report Yusuke Matsunaga (Kyushu Univ.) (15) 09:15 - 09:40 A Multiplexer Reduction Algorithm in High-level Synthesis for Distributed Register Architectures Tetsuya Endo, Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) (16) 09:40 - 10:05 Scheduling and Memory Binding in High Level Synthesis for FPGAs Yuki Sagawa, Tsuyoshi Sadakata, Yusuke Matsunaga (Kyusyu Univ.) ----- Break ( 10 min. ) ----- ---------------------------------------- Thu, Jan 17 AM (10:15 - 11:55) ---------------------------------------- (17) 10:15 - 10:40 Improvement in data communication between PEs for SIMD type processor MX core Yuta Mizokami, Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ) (18) 10:40 - 11:05 Development of Parallel Volume Rendering Accelerator VisA and its Preliminary Implementation Takahiro Kawahara, Shinobu Miwa, Hajime Shimada (Kyoto Univ.), Shin-ichiro Mori (Univ. of Fukui), Shinji Tomita (Kyoto Univ.) (19) 11:05 - 11:30 Implementation of 3-D Dynamically Reconfiguarable Device using Inter-Chip Wireless Communication Shotaro Saito, Yasufumi Sugimori, Yoshinori Kohama, Tadahiro Kuroda, Yohei Hasegawa, Hideharu Amano (Keio Univ.) (20) 11:30 - 11:55 An effective data I/O mechanism utilizing FIFOs for an array processor Yuusuke Nomoto, Yuka Sato, Toshiaki Miyazaki (Univ. of Aizu) ----- Break ( 60 min. ) ----- ---------------------------------------- Thu, Jan 17 PM (12:55 - 15:25) ---------------------------------------- (21) 12:55 - 13:20 Analysis of retention time under continuous reconfiguration of a DORGA Daisaku Seto, Minoru Watanabe (Shizuoka Univ.) (22) 13:20 - 13:45 A fast optical reconfiguration experiment of a dynamic optically reconfigurable gate array Mao Nakajima, Minoru Watanabe (Shizuoka Univ.) (23) 13:45 - 14:10 Fault tolerance analysis for holographic memories in optically reconfigurable gate arrays. Kouji Shinohara, Minoru Watanabe (Shizuoka Univ.) (24) 14:10 - 14:35 A Tile Based Dynamically Reconfigurable Architecture with Dual ALU-array/RISC Processor Operating Mode Capability Shin'ichi Kouyama, Masayuki Hiromoto, Hiroyuki Ochi (Kyoto Univ.), Yukihiro Nakamura (Ritsumeikan Univ.) (25) 14:35 - 15:00 Functionally-partitioned JPEG decoder for partial dynamic reconfiguration Taiichiro Yatsunami, Hideaki Yoshihiro, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) (26) 15:00 - 15:25 A Method for Saving and Restoring Context Data of Hardware Tasks on the Dynamically Reconfigurable Processor Vu Manh Tuan, Hideharu Amano (Keio Univ.) ----- Break ( 10 min. ) ----- ---------------------------------------- Thu, Jan 17 PM (15:35 - 18:05) ---------------------------------------- (27) 15:35 - 16:00 An L1 Data Cache Optimization Algorithm for Application Processor Cores Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) (28) 16:00 - 16:25 A Processor Kernel Generation Method for Application Processors Toshihiro Hiura, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) (29) 16:25 - 16:50 A Hybrid Design Space Exploration Approach for a Coarse-Grained Reconfigurable Accelerator Farhad Mehdipour (Kyushu Univ.), Hamid Noori (ISIT), Hiroaki Honda, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) (30) 16:50 - 17:15 VLIW Extension of Software Development Environment Construction Tool ArchC Takanori Morimoto (Kwansei Gakuin Univ.), Takahiro Kumura (NEC), Nagisa Ishiura (Kwansei Gakuin Univ.), Masao Ikekawa (NEC), Masaharu Imai (Osaka Univ.) (31) 17:15 - 17:40 Hardware Consious Style: a C Language Style for Hardware Design Kaiyi Mao, Hideharu Amano, Satoshi Tsutsumi, Vasutan Tunbunheng (Keio Univ.) (32) 17:40 - 18:05 C to HDL compiler for rapid HW-SW co-simulation models Yasuhiro Ito, Yutaka Sugawara, Kei Hiraki (Tokyo Univ.) === Technical Committee on Computer Systems (CPSY) === # FUTURE SCHEDULE: Thu, Mar 27, 2008 - Fri, Mar 28, 2008: [Tue, Jan 22] Wed, Apr 23, 2008: Tokyo Univ. [Wed, Feb 20], Topics: Dependable Computing Systems, etc. # SECRETARY: Morihiro KUGA (Kumamoto Univ.) TEL +81-96-342-3647, FAX +81-96-342-3599 E-mail:      am  -u === Technical Committee on VLSI Design Technologies (VLD) === # FUTURE SCHEDULE: Wed, Mar 5, 2008 - Fri, Mar 7, 2008: TiRuRu [Wed, Dec 12], Topics: System-on-silicon design techniques and related VLSs # SECRETARY: Hiroyuki OCHI (Kyoto Univ.) E-mail:o  eek -uTel.075-753-4803 # ANNOUNCEMENT: # See also VLD's homepage: http://www.ieice.org/~vld/ === Technical Committee on Reconfigurable Systems (RECONF) === # SECRETARY: Yohei HORI (AIST) E-mail:   yaist TEL: +81-29-861-5080 (Ext.)55459 FAX: +81-29-861-5909 === Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) === # FUTURE SCHEDULE: Thu, Mar 27, 2008 - Fri, Mar 28, 2008: [Tue, Jan 22] Last modified: 2008-01-15 20:49:42 |
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