Mon, Feb 13 AM
10:00 - 10:50 |
| (1) |
10:00-10:25 |
Design of Dual Edge Triggered Flip-Flops and Application to Signal Delay Detection |
Yoshihiro Ohkawa, Yukiya Miura (TMU) |
| (2) |
10:25-10:50 |
An Evaluation of the Effects for Hardware Trojan Designs in AES Encryption Circuits |
Amy Ogita, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.) |
| |
10:50-11:05 |
Break ( 15 min. ) |
Mon, Feb 13 AM
11:05 - 12:20 |
| (3) |
11:05-11:30 |
Pattern Merging for Additional Path Delay Fault Detection with Transition Delay Fault Test |
Hiroaki Tanaka, Kohei Miyase, Kazunari Enokimoto, Xiaoqing Wen, Seiji Kajihara (Kyutech) |
| (4) |
11:30-11:55 |
Note on Layout-Aware High Accuracy Estimation of Fault Coverage |
Masayuki Arai, Yoshihiro Shimizu, Kazuhiko Iwasaki (Tokyo Metro. Univ.) |
| (5) |
11:55-12:20 |
A method to reduce shift-toggle rate for low power BIST |
Takaaki Kato, Senling Wang, Kohei Miyase, Yasuo Sato, Seiji Kajihara (KIT) |
| |
12:20-14:00 |
Lunch Break ( 100 min. ) |
Mon, Feb 13 PM
14:00 - 15:15 |
| (6) |
14:00-14:25 |
A new problem at Boundary-Scan testing
-- an internal disruption within IC during interconnect testing -- |
Shuichi Kameyama (Fujitsu & Ehime Univ.), Masayuki Baba (Fujitsu), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) |
| (7) |
14:25-14:50 |
A method to reduce the number of test patterns for transition faults using control point insertions |
Akihiko Takahashi, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ) |
| (8) |
14:50-15:15 |
A Test Generation Method for Synchronously Designed QDI Circuits |
Koki Uchida, Eri Murata (NAIST), Satoshi Ohtake (Oita Univ.), Yasuhiko Nakashima (NAIST) |
| |
15:15-15:30 |
Break ( 15 min. ) |
Mon, Feb 13 PM
15:30 - 16:45 |
| (9) |
15:30-15:55 |
An approach for adaptive determination of IDDQ testing criteria based on process parameter estimation |
Michihiro Shintani, Takashi Sato (Kyoto Univ.) |
| (10) |
15:55-16:20 |
Dynamic Test Scheduling for In-Field Aging Detection |
Yosuke Morinaga, Tomokazu Yoneda (NAIST), Hyunbean Yi (Hanbat National Univ.), Michiko Inoue (NAIST) |
| (11) |
16:20-16:45 |
Evaluation of a thermal and voltage estimation circuit for field test |
Yousuke Miyake, Yasuo Sato, Seiji Kajihara, Kohei Miyase (Kyutech), Yukiya Miura (TMU) |
:
f
ulty
ba-u