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=============================================== Technical Committee on Dependable Computing (DC) Chair: Tomohiro Yoneda (NII) Vice Chair: Seiji Kajihara (Kyushu Inst. of Tech.) Secretary: Masato Kitagami (Chiba Univ.), Tomohiro Nakamura (Hitachi) DATE: Mon, Feb 13, 2012 10:00 - 16:45 PLACE: TOPICS: ---------------------------------------- Mon, Feb 13 AM (10:00 - 10:50) ---------------------------------------- (1) 10:00 - 10:25 Design of Dual Edge Triggered Flip-Flops and Application to Signal Delay Detection Yoshihiro Ohkawa, Yukiya Miura (TMU) (2) 10:25 - 10:50 An Evaluation of the Effects for Hardware Trojan Designs in AES Encryption Circuits Amy Ogita, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.) ----- Break ( 15 min. ) ----- ---------------------------------------- Mon, Feb 13 AM (11:05 - 12:20) ---------------------------------------- (3) 11:05 - 11:30 Pattern Merging for Additional Path Delay Fault Detection with Transition Delay Fault Test Hiroaki Tanaka, Kohei Miyase, Kazunari Enokimoto, Xiaoqing Wen, Seiji Kajihara (Kyutech) (4) 11:30 - 11:55 Note on Layout-Aware High Accuracy Estimation of Fault Coverage Masayuki Arai, Yoshihiro Shimizu, Kazuhiko Iwasaki (Tokyo Metro. Univ.) (5) 11:55 - 12:20 A method to reduce shift-toggle rate for low power BIST Takaaki Kato, Senling Wang, Kohei Miyase, Yasuo Sato, Seiji Kajihara (KIT) ----- Lunch Break ( 100 min. ) ----- ---------------------------------------- Mon, Feb 13 PM (14:00 - 15:15) ---------------------------------------- (6) 14:00 - 14:25 A new problem at Boundary-Scan testing -- an internal disruption within IC during interconnect testing -- Shuichi Kameyama (Fujitsu & Ehime Univ.), Masayuki Baba (Fujitsu), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) (7) 14:25 - 14:50 A method to reduce the number of test patterns for transition faults using control point insertions Akihiko Takahashi, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ) (8) 14:50 - 15:15 A Test Generation Method for Synchronously Designed QDI Circuits Koki Uchida, Eri Murata (NAIST), Satoshi Ohtake (Oita Univ.), Yasuhiko Nakashima (NAIST) ----- Break ( 15 min. ) ----- ---------------------------------------- Mon, Feb 13 PM (15:30 - 16:45) ---------------------------------------- (9) 15:30 - 15:55 An approach for adaptive determination of IDDQ testing criteria based on process parameter estimation Michihiro Shintani, Takashi Sato (Kyoto Univ.) (10) 15:55 - 16:20 Dynamic Test Scheduling for In-Field Aging Detection Yosuke Morinaga, Tomokazu Yoneda (NAIST), Hyunbean Yi (Hanbat National Univ.), Michiko Inoue (NAIST) (11) 16:20 - 16:45 Evaluation of a thermal and voltage estimation circuit for field test Yousuke Miyake, Yasuo Sato, Seiji Kajihara, Kohei Miyase (Kyutech), Yukiya Miura (TMU) # Information for speakers General Talk will have 20 minutes for presentation and 5 minutes for discussion. === Technical Committee on Dependable Computing (DC) === # FUTURE SCHEDULE: Fri, Mar 2, 2012 - Sat, Mar 3, 2012: [Mon, Jan 16] Tue, Apr 10, 2012: [Wed, Feb 15] Mon, May 28, 2012 - Wed, May 30, 2012: Kitakyushu International Conference Center , Topics: LSI and System Workshop 2012 # SECRETARY: Masato Kitakami Graduate School of Advanced Integration Science, Chiba University 1-33 Yayoi-cho Inage-ku, Chiba 263-8522 JAPAN TEL/FAX +43.290.3039 E-mail:     f ulty  ba-u Last modified: 2011-12-15 15:29:59 |
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