ken-system: Advance Program - 2013-05-VLD-IPSJ-SLDM

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Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)

[schedule] [select]

Chair		Michiaki Muraoka (Kochi Univ.)
Secretary		Hiroaki Komatsu (Fujitsu), Naoki Iwata (Sony), Nozomu Togawa (Waseda Univ.)

Technical Committee on VLSI Design Technologies (VLD)

[schedule] [select]

Chair		Akihisa Yamada (Sharp)
Vice Chair		Makoto Ikeda (Univ. of Tokyo)
Secretary		Takashi Takenaka (NEC), Shigetoshi Nakatake (Univ. of Kitakyushu)

Conference Date	Thu, May 16, 2013 09:00 - 16:50
Topics	System Design, etc.
Conference Place

Thu, May 16 AM Chair: Yasuhiro Takashima 09:00 - 10:15
(1) VLD	09:00-09:25	Performance-driven SRAM Macro Design with Parameterized Cell Considering Layout-dependent Effects	Yu Zhang, Shigetoshi Nakatake (Univ. of Kitakyushu)
(2) VLD	09:25-09:50	A Floorplan Method by Simulated Annealing and Sequence-pair for Asynchronous Circuits with Bundled-data Implementation	Minoru Iizuka, Hiroshi Saito (Univ. of Aizu)
(3) VLD	09:50-10:15	A Longest Path Algorithm for Differential Pair Net Considering Connectivity	Koji Yamazaki, Yukihide Kohira (Univ. of Aizu)
	10:15-10:25	Break ( 10 min. )
Thu, May 16 AM Chair: Michiaki Muraoka 10:25 - 11:40
(4)	10:25-10:50
(5)	10:50-11:15
(6)	11:15-11:40
	11:40-13:00	Break ( 80 min. )
Thu, May 16 PM Chair: Makoto Ikeda 13:00 - 14:00
(7) VLD	13:00-14:00	[Invited Talk] A Note on Routing and Placement	Yoji Kajitani (JAIST)
	14:00-14:10	Break ( 10 min. )
Thu, May 16 PM Chair: Atsushi Takahashi 14:10 - 15:25
(8) VLD	14:10-14:35	Level Converter Design for Ultra Low Voltage Operation in Silicon-on-Thin-BOX MOSFET	Shohei Nakamura, Kimiyoshi Usami (Shibaura Inst. of Tech.)
(9) VLD	14:35-15:00	A Linear Interpolation Unit Using Selector Logics	Masashi Shio, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
(10) VLD	15:00-15:25	Data Dependence Relaxation Techniques for Reducing Iteration Intervals in Pipelined Loops	Shingo Kusakabe, Kenshu Seto (Tokyo City Univ.)
	15:25-15:35	Break ( 10 min. )
Thu, May 16 PM Chair: Makoto Sugihara 15:35 - 16:50
(11) VLD	15:35-16:00	Scan-based Attack against Trivium Stream Cipher Using Scan Signatures	Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
(12) VLD	16:00-16:25	A Zero Time and Area Overhead Fault-Secure High-Level Synthesis Algorithm for RDR Architectures	Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
(13) VLD	16:25-16:50	SoC System Design Methodology with Fully-Coherent Cache	Kodai Moritaka (NAIST), Hiroaki Yoshida, Mitsuru Tomono (FLA), Yasuhiko Nakashima (NAIST)

Announcement for Speakers
General Talk	Each speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
IPSJ-SLDM	Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [Latest Schedule]
	Contact Address	Nozomu Togawa (Waseda University) Email sldm2012g
	Announcement	Please see the IPSJ-SLDM page below: http://www.sig-sldm.org/
VLD	Technical Committee on VLSI Design Technologies (VLD) [Latest Schedule]
	Contact Address	Takeshi Takenaka (NEC) E-: ajc Tel: 044-431-7194
	Announcement	See also VLD's homepage: http://www.ieice.org/~vld/