Fri, Jun 20 PM
13:15 - 14:55 |
| (1) |
13:15-13:40 |
Development of a delay time measurement circuit by inserting buffers |
Takuya Yamamoto, Yukiya Miura (Tokyo Metropolitan Univ.) |
| (2) |
13:40-14:05 |
A method of LSI degradation estimation using ring oscillators |
Tatsunori Ikeda, Yukiya Miura (Tokyo Metropolitan Univ.) |
| (3) |
14:05-14:30 |
A X-Filling Method for Low-Capture-Power Scan Test Generation |
Fuqiang Li, Xiaoqing Wen, Kohei Miyase, Stefan Holst, Seiji Kajihara (Kyushu Inst. of Tech.) |
| (4) |
14:30-14:55 |
Capture Power Evaluation for A Low Power BIST Method Using A TEG Chip |
Toshiya Nishida (Kyushu Inst. of Tech.), Senling Wang (Ehime Univ.), Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.) |
| |
14:55-15:10 |
Break ( 15 min. ) |
Fri, Jun 20 PM
15:10 - 16:50 |
| (5) |
15:10-15:35 |
A Fault Tolerant Response Analyzer for Built-in Self-test |
Yuki Fukazawa (Mie Univ.), Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) |
| (6) |
15:35-16:00 |
Floating-point Multiplier with Reduced Precision Error Checking by Partial Duplication |
Nobutaka Kito (Chukyo Univ.), Kazushi Akimoto, Naofumi Takagi (Kyoto Univ.) |
| (7) |
16:00-16:25 |
A Binding Method for Hierarchical Testability Using Results of Test Environment Generation |
Jun Nishimaki, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) |
| (8) |
16:25-16:50 |
An evaluation for Testability of Functional k-Time Expansion Models |
Tetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) |