Tue, May 29 AM Image Processing (1)
Chair: Kentaro Sano (Tohoku Univ.)
09:00 - 10:15 |
| (1) |
09:00-09:25 |
An Acceleration of a Graph Cut Segmentation with FPGA |
Daichi Kobori, Tsutomu Maruyama (Univ. of Tsukuba) |
| (2) |
09:25-09:50 |
An Imaging Device Control System |
Toru Yabuki, Yoshiki Yamaguchi, Yuetsu Kodama (Univ. of Tsukuba) |
| (3) |
09:50-10:15 |
FPGA implementation of a video-based real-time pupil detection method |
Yuma Hatanaka, Keisuke Dohi, Kazuhiro Negi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki City Univ) |
| |
10:15-10:35 |
Break ( 20 min. ) |
Tue, May 29 AM Device Architecture and Performance Assessment Study
Chair: Yuetsu Kodama (Univ. of Tsukuba)
10:35 - 11:50 |
| (4) |
10:35-11:00 |
A study on memory controller of MuCCRA-3: Dynamically Reconfigurable Processor Array |
Toru Katagiri, Kazuei Hironaka, Hideharu Amano (Keio Univ.) |
| (5) |
11:00-11:25 |
Development of a demonstration system for Ultra-low-power FPGA with Fine-Grained Field-Programmable Threshold Voltage Control |
Takashi Kawanami (KIT), Masakazu Hioki (AIST), Yohei Matsumoto (Kaiyo Univ.), Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST) |
| (6) |
11:25-11:50 |
Optimization of PE Array Interconnection on CMA to Reduce Configuration Data |
Rie Uno (keio Univ.), Nobuaki Ozaki, Hideharu Amano (Keio Univ.) |
| |
11:50-13:10 |
Lunch Break ( 80 min. ) |
Tue, May 29 PM HPC on Reconfigurable Hardware
Chair: Tsutomu Maruyama (Univ. of Tsukuba)
13:10 - 14:50 |
| (7) |
13:10-13:35 |
Implementation and Evaluation of FPGA-based Data Compression Hardware of Floating-Point Data-Stream |
Tomohiro Ueno, Yoshiaki Kono, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.) |
| (8) |
13:35-14:00 |
An FPGA Implementation for a 3-layer Perceptron with the FDFM Processor Core Approach |
Yuki Agou, Yasuaki Ito, Koji Nakano (Hiroshima Univ.) |
| (9) |
14:00-14:25 |
Implementation of Square Root Calculator on Reconfigurable Processor DS-HIE |
Takashi Ueda, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.) |
| (10) |
14:25-14:50 |
Scalability Analysis of Tightly-Coupled FPGA-Cluster for Lattice Boltzmann Computation |
Yoshiaki Kono, Kentaro Sano, Ryotaro Chiba, Satoru Yamamoto (Tohoku Univ.) |
| |
14:50-15:10 |
Break ( 20 min. ) |
Tue, May 29 PM Reconfigurable Application (1)
Chair: Yoshiki Yamaguchi (Univ. of Tsukuba)
15:10 - 16:25 |
| (11) |
15:10-15:35 |
Hard error avoidance for TMR module using dynamic relocation in an FPGA |
Hiroki Tanaka, Yoshihiro Ichinomiya, Sadaki Usagawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
| (12) |
15:35-16:00 |
a design of an interconnection system of modules and a control unit of reconfiguration for embedded systems utilizing dynamic reconfiguration |
Tomokazu Mizuno, Yoshiaki Kida, Ryo Kamide, Shin Terada, Mitsuyoshi Tokuda, Tomonori Izumi (Ritsumeikan Univ.) |
| (13) |
16:00-16:25 |
An Efficient Fault Detection and Avoidance Technique for FPGA Interconnects |
Yuuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) |
| |
16:25-16:45 |
Break ( 20 min. ) |
Tue, May 29 PM Reconfigurable Application (2)
Chair: Yohei Hori (AIST)
16:45 - 18:00 |
| (14) |
16:45-17:10 |
Implementation and evaluation of the AES/ADPCM on STP and FPGA with Behavioral Synthesis |
Yukihito Ishida, Seiya Shibata, Yuki Ando, Shinya Honda, Hiroaki Takada, Masato Edahiro (Nagoya Univ) |
| (15) |
17:10-17:35 |
Implementation of delay control methods for FPGA-based digital DC-DC Converters |
Yoshihiko Yamabe, Kanako Nakashima, Keisuke Dohi, Kazuma Hamawaki, Kentaro Yamashita, Kazuhiro Kajiwara, Fujio Kurokawa, Yuichiro Shibata, Kiyoshi Oguri (Univ.) |
| (16) |
17:35-18:00 |
Development of Application for Heterogeneous Multi-Core Processor |
Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano (Keio Univ.), Ryuichi Sakamoto, Mitaro Namiki (Tkyo Univ. of Agri. and Tech.) |
Wed, May 30 AM Image Processing (2)
Chair: Tomonori Izumi (Ritsumeikan Univ.)
09:00 - 10:15 |
| (17) |
09:00-09:25 |
AN FPGA ACCELERATION OF A LEVEL SET SEGMENTATION METHOD |
Haruhisa Tsuyama, Tsutomu Maruyama (Tsukuba Univ.) |
| (18) |
09:25-09:50 |
Proposal and Evaluation of photon mapping acceleration using FPGA |
Takuya Kuhara, Masato Yoshimi, Mitsunori Miki (Doshisha Univ.) |
| (19) |
09:50-10:15 |
Real-time Corner and Polygon Detection System on FPGA |
Chunmeng Bi, Tsutomu Maruyama (Univ. of Tsukuba) |
| |
10:15-10:35 |
Break ( 20 min. ) |
Wed, May 30 AM High-Level Synthesis and Development Environment
Chair: Yuichiro Shibata(Nagasaki Univ.)
10:35 - 12:15 |
| (20) |
10:35-11:00 |
SOM-based FPGA Placement Method using Shimbel Index |
Tetsuro Hamada, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
| (21) |
11:00-11:25 |
A Study of HW/SW Co-design with JavaRock |
Takefumi Miyoshi, Satoshi Funada (e-trees) |
| (22) |
11:25-11:50 |
A Domain Specific Language and Toolchain for Runtime Binary Acceleration |
Takaaki Miyajima (Keio Univ.), David Thomas (Imperial), Hideharu Amano (Keio Univ.) |
| (23) |
11:50-12:15 |
A Hardware Implementation and an FPGA Prototyping of a Connect-6 Player Algorithm Using Impulse-C |
Naohisa Arakawa, Tomonori Izumi (Ritsumeikan Univ.) |
| |
12:15-13:15 |
Lunch Break ( 60 min. ) |
Wed, May 30 PM FPGA Design Contest
Chair: Hideharu Amano(Keio Univ.)
13:15 - 16:50 |
| (1) |
13:15-14:50 |
FPGA Design Contest
(opening session and Connect-6 preliminary round)
For details, please visit the following website:
http://www.cs.tsukuba.ac.jp/~yoshiki/FPGA/Contest_eng/ |
| |
14:50-15:00 |
Break ( 10 min. ) |
| (2) |
15:00-16:50 |
FPGA Design Contest
(Connect-6 final round and closing session) |
| |
16:50-17:15 |
Break ( 25 min. ) |
Wed, May 30 PM Industrial Keynote
17:15 - 18:15 |
| (1) |
17:15-18:15 |
DAPDNA: A Coarse-Grained Dynamically Reconfigurable Architecture
-- introduction of application examples and a new product --
Akifumi Watanabe(Tokyo Keiki, Inc.)
http://www.tokyo-keiki.co.jp/hyd/e/products/20120508_dap01.html |
Wed, May 30 PM FPGA Design Contest Award Ceremony
19:00 - 20:30 |
| (1) |
19:00-20:30 |
FPGA Design Contest: Poster Session and Awards Ceremony
http://www.isheart.org/HEART2012/
(The workshop site closes at 21:00.) |
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