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=============================================== Technical Committee on Reconfigurable Systems (RECONF) Chair: Hideharu Amano (Keio Univ.) Vice Chair: Nobuki Kajihara (NEC), Akira Nagoya (Okayama Univ.) Secretary: Masahiro Iida (Kumamoto Univ.), Tomonori Izumi (Ritsumeikan Univ.) Assistant: Yohei Hori (AIST) DATE: Thu, Sep 25, 2008 13:00 - 17:40 Fri, Sep 26, 2008 09:30 - 14:20 PLACE: Tsushima Campus, Okayama University(1-1-1, Tsushima-naka, Okayama-shi, 700-8530, Japan. Prof. Akira Nagoya) TOPICS: ---------------------------------------- Thu, Sep 25 PM (13:00 - 15:00) ---------------------------------------- (1) 13:00 - 13:30 Acceleration of two-dimensional liquid simulation using FPGAs Anna Sato, Yuichi Okuyama (Aizu Univ), Tsuyoshi Hamada (Nagasaki Univ), Junji Kitamichi, Kenichi Kuroda (Aizu Univ) (2) 13:30 - 14:00 Implementation of JPEG Encoder on Dynamically Reconfigurable Processor and its Evaluation Naomichi Furushima, Nobuya Watanabe, Akira Nagoya (Okayama Univ) (3) 14:00 - 14:30 An Implementation of road sign recognition algorithm using levenshtein distance on FPGA Souichi Shimizu (Keio Univ.), Yoshiaki Ajioka (Ecchandesu Inc.), Masatoshi Arai, Daisuke Konno, Tomomichi Nanba (CalsonicKansei Co.), Hideharu Amano (Keio Univ.) (4) 14:30 - 15:00 An automatic combine algorithm of arithmetic pipelines for an FPGA-based biochemical simulator focused on similarities of rate law functions Hideki Yamada, Tomoya Ishimori, Yuichiro Shibata (Nagasaki Univ.), Yasunori Osana, Masato Yoshimi, Yuri Nishikawa, Hideharu Amano, Akira Funahashi (Keio Univ.), Noriko Hiroi (EMBL-EBI), Kiyoshi Oguri (Nagasaki Univ.) ----- Break ( 10 min. ) ----- ---------------------------------------- Thu, Sep 25 PM (15:10 - 16:40) ---------------------------------------- (5) 15:10 - 15:40 A Proposal of the Network Switch for a PC cluster that can change connection of Distributed Shared Memory Yoshimasa Ohnishi, Takaichi Yoshida (Kyushu Institute of Tech.) (6) 15:40 - 16:10 A Hardware Evaluation System for 2D Interconnection Networks by using an FPGA Based Network Card Akira Uejima, Masaki Kohata (Okayama Univ. of Sci.) (7) 16:10 - 16:40 An Implementation of Operating System Functions for a Distributed FPGA Cluster System Akira Kojima, Kazuya Tokunaga, Tetsuo Hironaka (Hiroshima City Univ.) ----- Break ( 20 min. ) ----- ---------------------------------------- Thu, Sep 25 PM (17:00 - 17:40) ---------------------------------------- (8) 17:00 - 17:40 [Invited Talk] Operating System and Reconfigurable Hardware Hideo Taniguchi (Okayama Univ.) ----- Party ( 120 min. ) ----- ---------------------------------------- Fri, Sep 26 AM (09:30 - 11:30) ---------------------------------------- (9) 09:30 - 10:00 A measurement of retention time of a dynamic optically reconfigurable gate array with large gates Daisaku Seto, Minoru Watanabe (Shizuoka Univ.) (10) 10:00 - 10:30 Development of Digit-serial Floating Point Units for Scientific Computation Engine Taiga Ban, Yu Shiraishi, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.) (11) 10:30 - 11:00 Exploration of Input Granularity Optimization for Variable Grain Logic Cell Masahiro Koga, Hiroshi Miura, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) (12) 11:00 - 11:30 Practice Evaluation Dynamically Reconfigurable Processor MuCCRA-2β Yoshiki Saito, Masaru Kato, Shotaro Saito, Toru Sano, Keiichiro Hirai, Takashi Nishimura, Takuro Nakamura, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano (Keio Univ.) ----- Lunch Break ( 65 min. ) ----- ----- Announce ( 15 min. ) ----- ---------------------------------------- Fri, Sep 26 PM (12:50 - 14:20) ---------------------------------------- (13) 12:50 - 13:20 A Case Study of Reliable Softcore Processor Using TMR Technique Yoshihiro Ichinomiya, Shiro Tanoue, Tomoyuki Ishida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) (14) 13:20 - 13:50 A study of a fault-tolerant System using TFT method Atsuhiro Kanamaru, Hiroyuki Kawai, Yoshiki Yamaguchi, Moritoshi Yasunaga (Univ. of Tsukuba) (15) 13:50 - 14:20 Consideration of Combinational Circuit Mapping Method for Reconfigurable Device MPLD Yutaro Oda, Kazuya Tanigawa, Tetsuo Hironaka, Naoki Hirakawa, Hiroaki Toguchi (Hiroshima City Univ.), Masayuki Sato (Taiyo Yuden) === Technical Committee on Reconfigurable Systems (RECONF) === # FUTURE SCHEDULE: Mon, Nov 17, 2008 - Wed, Nov 19, 2008: Kitakyushu Science and Research Park [Thu, Sep 11], Topics: Design Gaia 2008 ―New field of VLSI design― # SECRETARY: Yohei HORI (AIST) E-mail:    y aist TEL: +81-29-861-5080 (Ext.)55459 FAX: +81-29-861-5909 Last modified: 2008-09-26 16:52:58 |
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