IEICE Technical Committee Submission System
Advance Program
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top  Go Back   Prev VLD Conf / Next VLD Conf [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Makoto Ikeda (Univ. of Tokyo)
Vice Chair Toshiyuki Shibuya (Fujitsu Labs.)
Secretary Shigetoshi Nakatake (Univ. of Kitakyushu), Noriyuki Minegishi (Mitsubishi Electric)

Technical Committee on Computer Systems (CPSY) [schedule] [select]
Chair Tsutomu Yoshinaga (Univ. of Electro-Comm.)
Vice Chair Akira Asato (Fujitsu), Yasuhiko Nakajima (NAIST)
Secretary Koji Nakano (Hiroshima Univ.), Hidetsugu Irie (Univ. of Electro-Comm.)
Assistant Hiroaki Inoue (NEC), Takeshi Ohkawa (Utsunomiya Univ.)

Technical Committee on Reconfigurable Systems (RECONF) [schedule] [select]
Chair Tetsuo Hironaka (Hiroshima City Univ.)
Vice Chair Minoru Watanabe (Shizuoka Univ.), Masato Motomura (Hokkaido Univ.)
Secretary Yutaka Yamada (Toshiba), Yoshiki Yamaguchi (Univ. of Tsukuba)
Assistant Kazuya Tanikagawa (Hiroshima City Univ.)

Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [schedule] [select]
Chair Michiaki Muraoka (Kochi Univ.)
Secretary Naoki Iwata (Sony), Kotaro Shimamura (Hitachi), Makoto Sugihara (Kyushu Univ.)

Conference Date Tue, Jan 28, 2014 08:30 - 18:10
Wed, Jan 29, 2014 08:30 - 17:35
Topics FPGA Applications, etc 
Conference Place  
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

Tue, Jan 28 AM 
08:30 - 10:10
(1)
RECONF
08:30-08:55 Design and implementation of high-level synthesis compiler for stream computation VLD2013-102 CPSY2013-73 RECONF2013-56 Ryo Ito, Hayato Suzuki, Ryotaro Chiba, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.)
(2)
RECONF
08:55-09:20 A Unified Software/Reconfigurable Hardware Approach to Solving the Maximum Clique Problem of Large Graphs VLD2013-103 CPSY2013-74 RECONF2013-57 Chikako Miura, Shinobu Nagayama, Shin'ichi Wakabayashi, Masato Inagi (Hiroshima City Univ.)
(3)
RECONF
09:20-09:45 Artificial Intelligence of Blokus Duo on FPGA Using Cyber Work Bench VLD2013-104 CPSY2013-75 RECONF2013-58 Naru Sugimoto, Takaaki Miyajima, Takuya Kuhara, Takuji Mitsuishi, Hideharu Amano (Keio Univ.)
(4)
RECONF
09:45-10:10 a discussion on hardware architecture of SIFT algorithm for FPGAs utilizing a high-level synthesis tool VLD2013-105 CPSY2013-76 RECONF2013-59 Naohisa Arakawa, Lin Meng, Tomonori Izumi (Ritsumeikan Univ.)
  10:10-10:25 Break ( 15 min. )
Tue, Jan 28 AM 
10:25 - 12:05
(5)
CPSY
10:25-10:50 A Storing and Regenerating Signal Information in a Scalable Hardware System VLD2013-106 CPSY2013-77 RECONF2013-60 Yusuke Katoh, Daisuke Watanabe, Hironori Nakajo (Tokyo Univ. of Agriculture and Tech)
(6)
CPSY
10:50-11:15 Hardware Expansion Protocol in a Scalable Hardware System VLD2013-107 CPSY2013-78 RECONF2013-61 Daisuke Watanabe, Yusuke Katoh, Hironori Nakajo (Tokyo Univ. of Agriculture and Tech.)
(7)
CPSY
11:15-11:40 A FPGA/GPU cooperation in nodes communication using PEACH2 VLD2013-108 CPSY2013-79 RECONF2013-62 Takuya Kuhara, Takaaki Miyajima (Keio Univ.), Toshihiro Hanawa (Tokyo Univ.), Hideharu Amano (Keio Univ.), Taisuke Boku (Univ. of Tsukuba)
(8)
CPSY
11:40-12:05 Reduction Method of Asynchronous Circuits with Maximum Delay Loops using SDI Delay Assumption VLD2013-109 CPSY2013-80 RECONF2013-63 Tomoya Tasaki, Hiroto Kagotani, Yuji Sugiyama (Okayama Univ.)
  12:05-13:20 Lunch ( 75 min. )
Tue, Jan 28 PM 
13:20 - 14:20
(9) 13:20-14:20 [Invited Talk]
Research on VLSI Circuits
-- From Solving Problem to Creating Future --
VLD2013-110 CPSY2013-81 RECONF2013-64
Tadahiro Kuroda (Keio Univ.)
  14:20-14:35 Break ( 15 min. )
Tue, Jan 28 PM 
14:35 - 16:15
(10)
CPSY
14:35-15:00 The Improvement of Auto-Sharding in MongoDB with Priority-Chunk VLD2013-111 CPSY2013-82 RECONF2013-65 Yasuhiro Sato, Ryota Kawashima, Hiroshi Matsuo (Nagoya Inst. of Tech.)
(11)
CPSY
15:00-15:25 Improving the Preformance of Virtual Machine Live Migration by Ordering Memory Page Transfer on Access Pattern VLD2013-112 CPSY2013-83 RECONF2013-66 Shintaro Nakai, Ryota Kawashima, Hiroshi Matsuo (Nagoya Inst. of Tech.)
(12)
CPSY
15:25-15:50 A Vertical Link On/Off Algorithm for Wireless 3-D NoCs VLD2013-113 CPSY2013-84 RECONF2013-67 Go Matsumura (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano, Hiroki Matsutani (Keio Univ.)
(13)
CPSY
15:50-16:15 A Case for Low-Power Networks using FSO and On/Off Links VLD2013-114 CPSY2013-85 RECONF2013-68 Tomoya Ozaki (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano, Hiroki Matsutani (Keio Univ.)
  16:15-16:30 Break ( 15 min. )
Tue, Jan 28 PM 
16:30 - 18:10
(14)
RECONF
16:30-16:55 A 3D FPGA-Array "Vocalise" and its communication system. VLD2013-115 CPSY2013-86 RECONF2013-69 Yusuke Atsumari, Jiang Li, Hiromasa Kubo, Akihiro Sorimachi, Baku Ogasawara, Masatoshi Sekine (TUAT)
(15)
RECONF
16:55-17:20 An Image Recognition System with Multi-Resolutional Feature Learning on the 3D FPGA-Array "Vocalise" VLD2013-116 CPSY2013-87 RECONF2013-70 Baku Ogasawara, Satoru Yokota, Jiang Li, Yusuke Atsumari, Hiromasa Kubo, Masatoshi Sekine (TUAT)
(16)
RECONF
17:20-17:45 Double Caching Memcached Accelerator VLD2013-117 CPSY2013-88 RECONF2013-71 Eric Shun Fukuda, Tsunaki Sadahisa (Hokkaido Univ.), Hiroaki Inoue, Takashi Takenaka (NEC), Tetsuya Asai, Masato Motomura (Hokkaido Univ.)
(17)
RECONF
17:45-18:10 A study on module allocation in multi-FPGA systems VLD2013-118 CPSY2013-89 RECONF2013-72 Yusuke Hirai, Kazuaki Nakazato (Univ. of the Ryukyus), Mohamed Sofian bin Abu Talip, Mishra Dipikarani, Hideharu Amano (Keio Univ.), Naoyuki Fujita (JAXA), Yasunori Osana (Univ. of the Ryukyus)
Wed, Jan 29 AM 
08:30 - 10:10
(1)
CPSY
08:30-08:55 An Experimental Bit-Parallel Solution to Accelerate Smith-Waterman Algorithm VLD2013-119 CPSY2013-90 RECONF2013-73 Saori Sudo, Masato Yoshimi, Hidetsugu Irie, Tsutomu Yoshinaga (UEC)
(2)
CPSY
08:55-09:20 Evaluation of parallelization for multiple-precision Cyclic Vector Multiplication Algorithm using CUDA VLD2013-120 CPSY2013-91 RECONF2013-74 Satoshi Haramura, Hiroto Kagotani, Yasuyuki Nogami, Yuji Sugiyama (Okayama Univ.)
(3)
CPSY
09:20-09:45 Performance Evaluation of Graph Database using Multicore and GPU VLD2013-121 CPSY2013-92 RECONF2013-75 Shin Morishima, Hiroki Matsutani (Keio Univ.)
(4)
CPSY
09:45-10:10 An Efficient SIMD Instruction set for Motion Estimation Ken Miura, Takumi Inomata, Toshio Kondo, Takahiro Sasaki (Mie Univ.)
  10:10-10:25 Break ( 15 min. )
Wed, Jan 29 AM 
10:25 - 12:05
(5)
RECONF
10:25-10:50 Implementation of MuCCRA-4: Dynamically Reconfigurable Processor Array VLD2013-122 CPSY2013-93 RECONF2013-76 Toru Katagiri, Hideharu Amano (Keio Univ.)
(6)
RECONF
10:50-11:15 A configurable switch mechanism for random NoCs VLD2013-123 CPSY2013-94 RECONF2013-77 Seiichi Tade, Takahiro Kagami, Ryuta Kawano, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.)
(7)
RECONF
11:15-11:40 Implementation and Evaluation of Multi-stream Bandwidth Compressor VLD2013-124 CPSY2013-95 RECONF2013-78 Tomohiro Ueno, Ryo Ito, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.)
(8)
RECONF
11:40-12:05 Study of accelerator connection using the peripheral bus of OpenMSP430 VLD2013-125 CPSY2013-96 RECONF2013-79 Ayano Fukuju, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.)
  12:05-13:20 Lunch ( 75 min. )
Wed, Jan 29 PM 
13:20 - 14:35
(9)
VLD
13:20-13:45 A Locality-Driven Task Mapping Algorithm for Multi-FPGA Systems VLD2013-126 CPSY2013-97 RECONF2013-80 Hiroki Katano, SeungJu Lee, Nozomu Togawa (Waseda Univ.), Takashi Aoki, Yusuke Sekihara, Mamoru Nakanishi (NTT)
(10)
VLD
13:45-14:10 On Boolean Matching of LUT-based Circuits VLD2013-127 CPSY2013-98 RECONF2013-81 Yusuke Matsunaga (Kyushu Univ.)
(11)
VLD
14:10-14:35 Dynamic Operation Binding in Distributed Controller for Supporting Functional Units with Variable Latency VLD2013-128 CPSY2013-99 RECONF2013-82 Shinji Yamashita, Nagisa Ishiura (Kwansei Gakuin Univ.)
  14:35-14:50 Break ( 15 min. )
Wed, Jan 29 PM 
14:50 - 16:05
(12)
VLD
14:50-15:15 Prediction Model for Process Variation and BTI-Induced Degradation by Measurement Data on FPGA VLD2013-129 CPSY2013-100 RECONF2013-83 Michitarou Yabuuchi, Kazutoshi Kobayashi (Kyoto Inst. of Tech.)
(13)
VLD
15:15-15:40 A Reduction Method of Writing Operations to Non-volatile Memory by Keeping Data Difference for Low-Power Circuit Design VLD2013-130 CPSY2013-101 RECONF2013-84 Hiroyuki Shinohara, Masao Yanagisawa, Shinji Kimura (Waseda Univ.)
(14)
VLD
15:40-16:05 Methodology for NBTI measurement using an on-chip leakage monitor circuit VLD2013-131 CPSY2013-102 RECONF2013-85 Takaaki Sato, Kimiyoshi Usami (Shibaura Inst. of Tech.)
  16:05-16:20 Break ( 15 min. )
Wed, Jan 29 PM 
16:20 - 17:35
(15)
VLD
16:20-16:45 PerCUDA: CUDA Binding Framework for Perl VLD2013-132 CPSY2013-103 RECONF2013-86 Takayuki Fukumoto, Nagisa Ishiura (Kwansei Gakuin Univ.)
(16)
VLD
16:45-17:10 Binary Synthesis of Hardware Accelerator Tightly Coupled with CPU VLD2013-133 CPSY2013-104 RECONF2013-87 Shimpei Tamura, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Kanbara (ASTEM), Hiroyuki Tomiyama (Ritsumeikan Univ.)
(17) 17:10-17:35  

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address  
Announcement See also VLD's homepage:
http://www.ieice.org/~vld/
CPSY Technical Committee on Computer Systems (CPSY)   [Latest Schedule]
Contact Address  
RECONF Technical Committee on Reconfigurable Systems (RECONF)   [Latest Schedule]
Contact Address  
IPSJ-SLDM Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)   [Latest Schedule]
Contact Address  
Announcement Please see the IPSJ-SLDM page below:
http://www.sig-sldm.org/


Last modified: 2014-01-17 17:21:18


Notification: Mail addresses are partially hidden against SPAM.

[Download Paper's Information (in Japanese)] <-- Press download button after click here.
 
[Cover and Index of IEICE Technical Report by Issue]
 

[Presentation and Participation FAQ] (in Japanese)
 

[Return to VLD Schedule Page]   /   [Return to CPSY Schedule Page]   /   [Return to RECONF Schedule Page]   /   [Return to IPSJ-SLDM Schedule Page]   /  
 
 Go Top  Go Back   Prev VLD Conf / Next VLD Conf [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan