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Technical Committee on Dependable Computing (DC)
Chair: Michiko Inoue (NAIST) Vice Chair: Satoshi Fukumoto (Tokyo Metropolitan Univ.)
Secretary: Masayoshi Yoshimura (Kyoto Sangyo Univ.), Haruhiko Kaneko (Tokyo Inst. of Tech.)
DATE:
Tue, Feb 21, 2017 10:30 - 17:00
PLACE:
Kikai-Shinko-Kaikan Bldg.(Prof. Tomoo Inoue, Toshinori Hosokawa. +81-3-3434-8216)
TOPICS:
VLSI Design and Test, etc
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Tue, Feb 21 AM Low Power Testing (10:30 - 11:20)
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(1) 10:30 - 10:55
A dynamic test compaction method on low power oriented test generation using capture safe test vectors
Toshinori Hosokawa, Atsushi Hirai, Hiroshi Yamazaki, Masayuki Arai (Nihon Univ.)
(2) 10:55 - 11:20
IR-Drop Analysis on Different Power Supply Network Designs
Kohei Miyase, Kiichi Hamasaki (Kyutech), Matthias Sauer (University of Freiburg), Ilia Polian (University of Passau), Bernd Becker (University of Freiburg), Xiaoqing Wen, Seiji kajihara (Kyutech)
----- Break ( 15 min. ) -----
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Tue, Feb 21 AM Fault Diagnosis (11:35 - 12:25)
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(3) 11:35 - 12:00
Built-In Self Diagnosis Architecture for Logic Design
Keisuke Kagawa, Fumiya Yano, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Satoshi Ohtake (Oita Univ.)
(4) 12:00 - 12:25
An Approach to Performance Improvement of Machine Learning Based Fail Chip Discrimination
Daichi Yuruki, Satoshi Ohtake (Oita Univ), Yoshiyuki Nakamura (Renesas System Design)
----- Break ( 95 min. ) -----
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Tue, Feb 21 PM (14:00 - 14:50)
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(5) 14:00 - 14:25
Impact of Operational Unit Binding on Aging-induced Degradation in High-level Synthesis for Asynchronous Systems
Tsuyoshi Iwagaki, Kohta Itani, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
(6) 14:25 - 14:50
An Untestable Fault Identification Method for Sequential Circuits Based on SAT Using Unreachable States
Morito Niseki, Toshinori Hosokawa (Nihon Univ.), Msayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.)
----- Break ( 15 min. ) -----
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Tue, Feb 21 PM (15:05 - 15:55)
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(7) 15:05 - 15:30
A Method of Strongly Secure Scan Design Using Extended Shift Registers
Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ), Hideo Fujiwara (Osaka Gakuin Univ)
(8) 15:30 - 15:55
A Study of Message Efficient Avoidance Routing
Yusuke Sugiura, Tomoya Osuki, Kazuya Sakai, Satoshi Fukumoto (Tokyo Metropolitan Univ.)
----- Break ( 15 min. ) -----
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Tue, Feb 21 PM (16:10 - 17:00)
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(9) 16:10 - 16:35
Considerations on Characteristics of Ring Oscillators Implemented in FPGA
Kouhei Satou, Yukiya Miura (Tokyo Metropolitan Univ.)
(10) 16:35 - 17:00
Design for Evaluation of TSV based Interconnections in 3D-SIC
-- Interconnection Resistance Evaluation with Analog Boundary Scan --
Shuichi Kameyama (Ehime Univ./Fujitsu), Senling Wang, Hiroshi Takahashi (Ehime Univ.)
# Information for speakers
General Talk will have 20 minutes for presentation and 5 minutes for discussion.
=== Technical Committee on Dependable Computing (DC) ===
# FUTURE SCHEDULE:
Thu, Mar 9, 2017 - Fri, Mar 10, 2017: Kumejima Island [Fri, Jan 13], Topics: ETNET20167
Mon, May 15, 2017 - Tue, May 16, 2017: Institute of Industrial Science, University of Tokyo [unfixed], Topics: LSI and System Workshop 2017
Mon, May 22, 2017 - Wed, May 24, 2017: Noboribetsu-Onsen Dai-ichi-Takimoto-Kan [Fri, Mar 24], Topics: HotSPA2017: Reconfigurable System, Dependable Computing System, and General Topics
Last modified: 2017-01-11 08:06:54
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