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Technical Committee on Hardware Security (HWS) [schedule] [select]
Chair Makoto Ikeda (Univ. of Tokyo)
Vice Chair Yasuhisa Shimazaki (Renesas Electronics), Makoto Nagata (Kobe Univ.)
Secretary Takatsugu Ono (Kyushu Univ.), Junko Takahashi (NTT)

Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Daisuke Fukuda (Fujitsu Labs.)
Vice Chair Kazutoshi Kobayashi (Kyoto Inst. of Tech.)
Secretary Yuichi Sakurai (Hitachi), Daisuke Kanemoto (Osaka Univ.)
Assistant Takuma Nishimoto (Hitachi)

Conference Date Wed, Mar 3, 2021 10:00 - 16:50
Thu, Mar 4, 2021 09:30 - 17:40
Topics Design Technology for System-on-Silicon, Hardware Security, etc. 
Conference Place Online 
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Registration Fee This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on HWS, VLD.

  09:50-10:00 Opening Address ( 10 min. )
Wed, Mar 3 AM  VLD-1:Deep Learning
10:00 - 11:40
(1) 10:00-10:25 Energy Efficient Approximate Storing to MRAM for Deep Neural Network Tasks in Edge Computing VLD2020-67 HWS2020-42 Yoshinori Ono, Kimiyoshi Usami (SIT)
(2) 10:25-10:50 Evaluation on Approximate Multiplier for CNN Calculation VLD2020-68 HWS2020-43 Yuechuan Zhang, Masahiro Fujita, Takashi Matsumoto (UTokyo)
(3) 10:50-11:15 A performance and resources estimation of AI Inference circuit on FPGAs VLD2020-69 HWS2020-44 Ryo Yamamoto, Iwagawa Hidetoshi, Yoshihiro Ogawa (MELCO)
(4) 11:15-11:40 The Design and Development of of Quantized Neural Networks Library for Exact Hardware Emulation VLD2020-70 HWS2020-45 Masato Kiyama, Yasuhiro Nakahara, Motoki Amagasaki, Masahiro Iida (Kumamoto Univ.)
  11:40-13:00 Lunch Break ( 80 min. )
Wed, Mar 3 PM  VLD:Commemorative Lecture
13:00 - 14:15
(5) 13:00-13:25 [Memorial Lecture]
Scheduling Sparse Matrix-Vector Multiplication onto Parallel Communication Architecture VLD2020-71 HWS2020-46
Mingfei Yu, Ruitao Gao, Masahiro Fujita (Univ. Tokyo)
(6) 13:25-13:50 [Memorial Lecture]
Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization VLD2020-72 HWS2020-47
TaiYu Cheng (Osaka Univ.), Yutaka Masuda (Nagoya Univ.), Jun Nagayama, Yoichi Momiyama (Socionext Inc.), Jun Chen, Masanori Hashimoto (Osaka Univ.)
(7) 13:50-14:15 [Memorial Lecture]
Dynamical Decomposition and Mapping of MPMCT Gates to Nearest Neighbor Architectures VLD2020-73 HWS2020-48
Atsushi Matsuo, Wakaki Hattori, Shigeru Yamashita (Ritsumeikan University)
  14:15-14:30 Break ( 15 min. )
Wed, Mar 3 PM  VLD-2:Algorithm and Circuit System
14:30 - 15:45
(8) 14:30-14:55 Measurement of Voltage-variation-tolerant Temperature Sensor for Standard CMOS Chip with On-chip Solar Cell VLD2020-74 HWS2020-49 Shuto Murohara, Tatsuya Banno, Tomoya Kimura, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.)
(9) 14:55-15:20 Aggregating Service Functions in Full Hardware Implementation of RTOS-Based Systems VLD2020-75 HWS2020-50 Iori Muguruma, Nagisa Ishiura, Takuya Ando (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO)
(10) 15:20-15:45 Heuristic Algorithms for Dynamic Scheduling of Moldable Tasks in Multicore Embedded Systems VLD2020-76 HWS2020-51 Takuma Hikida, Hiroki Nishikawa, Hiroyuki Tomiyama (Ritsumeikan Univ.)
  15:45-16:00 Break ( 15 min. )
Wed, Mar 3 PM  Hardware Trojan・Security Chip
16:00 - 16:50
(11) 16:00-16:25 Highly Efficient Simulation Method to Find Hardware Trojans Hidden in Semiconductor Chips VLD2020-77 HWS2020-52 Kazuki Yasuda, Kazuki Monta, Daichi Nakagawa, Masaru Mashiba, Takuji Miki, Makoto Nagata (Kobe Univ.)
(12) 16:25-16:50 Counteracting Chip Transplantation Attack using Hologram on Epoxy Covering VLD2020-78 HWS2020-53 Takashi Sudo, Takeshi Sugawara (UEC)
Thu, Mar 4 AM  VLD-3:Design Technology
09:30 - 10:45
(13) 09:30-09:55 Design space exploration on low energy embedded multi-core processors VLD2020-79 HWS2020-54 Sayuri Onagi, Yuko Hara (Tokyo Tech)
(14) 09:55-10:20 High-level synthesis of approximate circuits with two-level accuracies VLD2020-80 HWS2020-55 Kenta Shirane, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama (Ritumeikan Univ.)
(15) 10:20-10:45 A Fundamental Study on Three-Dimensional Module Placement for Layered Three-Dimensional LSI VLD2020-81 HWS2020-56 Tomohiro Noguchi, Hindawi Omran, Mineo Kaneko (JAIST)
Thu, Mar 4 AM  VLD:Special Lecture
10:45 - 11:45
(16) 10:45-11:45 [Special Talk]
Efficient VLSI Layout Data Structures and Algorithms
-- a Brief Tutorial --
Shmuel Wimer (Bar-Ilan University)
  11:45-13:00 Lunch Break ( 75 min. )
Thu, Mar 4 PM  HWS-2:Design of Hardware
13:00 - 14:40
(17) 13:00-13:25 Design of Area-Efficient Response Generator for CMOS Image Sensor PUF VLD2020-82 HWS2020-57 Masanori Aoki, Shunsuke Okura, Masayoshi Shirahata, Takeshi Fujino (Ritsumeikan Univ.)
(18) 13:25-13:50 A Low-Latency Memory Encryption Scheme with Tweakable Block Cipher and Its Hardware Design VLD2020-83 HWS2020-58 Maya Oda, Rei Ueno, Naofumi Homma (Tohoku Univ.), Akiko Inoue, Kazuhiko Minematsu (NEC)
(19) 13:50-14:15 Design and Evaluation of Efficient AES S-box Hardware with Optimization of Linear Mappings VLD2020-84 HWS2020-59 Ayano Nakashima, Rei Ueno, Naofumi Homma (Tohoku Univ.)
(20) 14:15-14:40 Experiments of Data Authenticity Verification in Multi-Node IoT Systems Using Elliptic Curve Digital Signature Chips VLD2020-85 HWS2020-60 Yuya Takahashi, Takuya Matsumaru, Kazuki Monta (Kobe Univ.), Toshihiro Sato, Takaaki Okidono (ECSEC Lab), Takuji Miki, Noriyuki Miura, Makoto Nagata (Kobe Univ.)
  14:40-14:55 Break ( 15 min. )
Thu, Mar 4 PM  HWS-3:Side-Channel Attacks
14:55 - 15:45
(21) 14:55-15:20 FPGA Implementation of Lightweight Cipher Chaskey through High-Level Synthesis and its Evaluation of Side-Channel Attack Resistance VLD2020-86 HWS2020-61 Saya Inagaki, Mingyu Yang (Tokyo Tech), Yang Li, Kazuo Sakiyama (UEC), Yuko Hara (Tokyo Tech)
(22) 15:20-15:45 Power Analysis Attack on a Unrolled Midori128 and its Evaluation VLD2020-87 HWS2020-62 Shu Takemoto, Yoshiya Ikezaki, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.)
  15:45-16:00 Break ( 15 min. )
Thu, Mar 4 PM  HWS-4:System Security
16:00 - 17:40
(23) 16:00-16:25 Survey on intrusion detection system for Vehicle Security Techniques VLD2020-88 HWS2020-63 Ayaka Matsushita, Takao Okubo (IISEC)
(24) 16:25-16:50 Security Evaluation of an IoT Cloud Service against Local Attacks VLD2020-89 HWS2020-64 Makoto Ishida, Takeshi Sugawara (UEC)
(25) 16:50-17:15 Screen Information Reconstruction from High Resolution Displays Focusing on Multiple Leakage Frequencies VLD2020-90 HWS2020-65 Kimihiro Arai, Daisuke Fujimoto, Yuichi Hayashi (NAIST)
(26) 17:15-17:40 Fundamental Study on Evaluation of EM Information Leakage from Smart Speakers with Different Installation Environments and Its Countermeasures VLD2020-91 HWS2020-66 Shogo Fukushima, Daisuke Fujimoto, Yuichi Hayashi (NAIST)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
HWS Technical Committee on Hardware Security (HWS)   [Latest Schedule]
Contact Address Takatsugu Ono(Kyushu University), Junko Takahashi(NTT)
E-:hws-c 
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Yuichi Sakurai (Hitachi)
E-: iixj 
Announcement See also VLD's homepage:
http://www.ieice.org/~vld/


Last modified: 2021-02-27 09:33:08


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