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Technical Committee on Reconfigurable Systems (RECONF)
Chair: Akira Nagoya (Okayama Univ.)
Vice Chair: Shorin Kyo (Renesas), Tetsuo Hironaka (Hiroshima City Univ.)
Secretary: Yohei Hori (AIST), Tomonori Izumi (Ritsumeikan Univ.)
Assistant: Nobuya Watanabe (Okayama Univ.)

DATE:
Thu, May 12, 2011 10:20 - 17:20
Fri, May 13, 2011 09:15 - 15:10

PLACE:

TOPICS:
Reconfigurable Systems, etc.

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Thu, May 12 AM (10:20 - 12:00)
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(1) 10:20 - 10:45
Resource Sharing in FPGA and Implementation of Face-Angle Detection Algorithm using Impulse C
Takaaki Miyajima (Keio Univ.), Masatoshi Arai (Calsonic), Hideharu Amano (Keio Univ.)

(2) 10:45 - 11:10
Pattern Compression of FAST Corner Detection and its FPGA Implementation
Keisuke Dohi, Yuji Yorita, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.)

(3) 11:10 - 11:35
An Implementation of Mean Shift Filter on FPGA
Dang Ba Khac Trieu, Tsutomu Maruyama (University of Tsukuba)

(4) 11:35 - 12:00
A real-time stereo vision system using a tree-structured dynamic programming on FPGA
Minxi Jin, Tsutomu Maruyama (Tsukuba Univ.)

----- Lunch Break ( 90 min. ) -----

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Thu, May 12 PM (13:30 - 14:45)
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(5) 13:30 - 13:55
Context Synchronization Method for Reliable Softcore Processor System
Makoto Fujino, Noritaka Kai, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)

(6) 13:55 - 14:20
Evaluation of reliability enhancement achieved by fault avoidance on dynamically reconfigurable architectures
Hiroaki Konoura (Osaka Univ.), Yukio Mitsuyama (Kochi Univ. Tech.), Masanori Hashimoto, Takao Onoye (Osaka Univ.)

(7) 14:20 - 14:45
Implementation of Bundled-Data Asynchronous Circuits on FPGA and thier Performance Evaluation
Tadashi Okabe (TIRI)

----- Break ( 15 min. ) -----

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Thu, May 12 PM (15:00 - 16:15)
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(8) 15:00 - 15:25
Design and Implementation of a Portable Framework for PCI Express Interface
Shoichi Igarashi, Ryuhei Morita, Yuichi Okuyama (Univ. of Aizu), Tsuyoshi Hamada (Nagasaki Univ.), Junji Kitamichi, Kenichi Kuroda (Univ. of Aizu)

(9) 15:25 - 15:50
Development of Wireless Video Transmission Equipment in 5GHz MIMO-OFDM Using FPGA
Jun Takizawa, Takaya Kaji, Shingo Yoshizawa (Hokkaido Univ.), Takashi Gunji, Morio Tawarayama (Mitubishi Denki Tokki System), Yoshikazu Miyanaga (Hokkaido Univ.)

(10) 15:50 - 16:15
A Virus Scanning Engine Using a 4IGU Emulator and an MPU
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (KIT)

----- Break ( 15 min. ) -----

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Thu, May 12 PM (16:30 - 17:20)
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(11) 16:30 - 17:20
[Invited Talk]
ERATO MINATO Discrete Structure Manipulation System Project and Current Work on System Design Area
Shin-ichi Minato (Hokkaido Univ.)

----- Banquet -----

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Fri, May 13 AM (09:15 - 10:30)
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(12) 09:15 - 09:40
*
Akira Fukui, Masahiro Fujita (Tokyo University)

(13) 09:40 - 10:05
Implementation of Out-Of-Order Execution System for Acceleration of Surface Integral in FaSTAR
Takayuki Akamine, Kenta Inakagata (Keio Univ.), Yasunori Osana (Ryukyu Univ.), Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.)

(14) 10:05 - 10:30
Evaluation of Scalable Streaming Array for High-Performance Stencil Computation with Low Memory Bandwidth
Kentaro Sano (Tohoku Univ.), Yoshiaki Hatsuda (Kobo Co. Ltd), Yoshiaki Kono, Satoru Yamamoto (Tohoku Univ.)

----- Break ( 15 min. ) -----

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Fri, May 13 AM (10:45 - 12:00)
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(15) 10:45 - 11:10
Optimization of Application Programs of SLD-1 : A Low Power Accelarator
Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Tech. Univ.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Tokyo Univ. of Electro-Communication)

(16) 11:10 - 11:35
Implementation and Evaluation of a low power accelerator SLD-2
Mai Izawa, Nobuaki Ozaki, Yoshihiro Yasuda, Masayuki Kimura, Hideharu Amano (Keio Univ.)

(17) 11:35 - 12:00
Power Consumption Evaluation of a Dynamically Reconfigurable Multi-cryptoprocessor on Virtex-5 FPGA
Yohei Hori, Toshihiro Katashita, Akashi Satoh (AIST)

----- Lunch Break ( 90 min. ) -----

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Fri, May 13 PM (13:30 - 15:10)
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(18) 13:30 - 13:55
A Implementation of Programmable Re-Ordering Unit for Array Processor
Tomoyoshi Kobori, Nozomi Ishihara, Katsutoshi Seki, Masao Ikekawa (NEC)

(19) 13:55 - 14:20
A Homogeneous Routing Architecture for Efficient FPGA Design
Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)

(20) 14:20 - 14:45
A Novel Abridged Adaptive LUT Architecture with Few Configulation Memories
Ken Taura, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)

(21) 14:45 - 15:10
A 256-context optically reconfiguration using a digital mirror device
Yuichiro Yamaji, Minoru Watanabe (Shizuoka Univ.)

# Information for speakers
General Talk will have 20 minutes for presentation and 5 minutes for discussion.

=== Technical Committee on Reconfigurable Systems (RECONF) ===

# SECRETARY:
Tomonori Izumi (Ritsumeikan University)
Email: t-i