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=============================================== Technical Committee on Dependable Computing (DC) Chair: Takashi Aikyo (STARC) Vice Chair: Tomohiro Yoneda (NII) Secretary: Masato Kitagami (Chiba Univ.), Michinobu Nakao (Renesas) =============================================== Technical Committee on Computer Systems (CPSY) Chair: Toshinori Sueyoshi (Kumamoto Univ.) Vice Chair: Syuuichi Sakai (Univ. of Tokyo), Yoshio Miki (Hitachi) Secretary: Morihiro Kuga (Kumamoto Univ.), Akira Asato (Fujitsu Labs.) Assistant: Hidetsugu Irie (Univ. of Tokyo) DATE: Tue, Apr 21, 2009 11:00 - 17:00 PLACE: TOPICS: Dependable Computer Systems, Security Technology, etc. ---------------------------------------- Tue, Apr 21 AM (11:00 - 11:50) ---------------------------------------- (1) 11:00 - 11:25 Highly Reliable Sequential Circuits Considering Multiple Simultaneous Transient Faults Hideo Kohinata, Kohei Marumoto, Masayuki Arai, Satoshi Fukumoto (Tokyo Metropolitan Univ.) (2) 11:25 - 11:50 A Development Process with A Model Checking Criterion Michitaka Inui (Mitsubishi Electric Micro-Computer Application Software Corp.), Nobukazu Yoshioka (NII) ----- Lunch Break ( 70 min. ) ----- ---------------------------------------- Tue, Apr 21 PM (13:00 - 14:15) ---------------------------------------- (3) 13:00 - 13:25 Evaluation of a Metropolis Algorithm for Constructing Unstructured Overlay Networks Tatsushi Takamura, Tatsuhiro Tsuchiya, Tohru Kikuno (Osaka Univ.) (4) 13:25 - 13:50 A Security Data-Flow Analysis in the Secure Software Development Environment DFITS Fukutomo Nakanishi, Ryotaro Hayashi, Hiroyoshi Haruki, Yurie Fujimatsu, Mikio Hashimoto (Toshiba Corp.) (5) 13:50 - 14:15 Fast Soft Error Rate Estimation for Circuits Containing Arithmetic Units Motoharu Hirata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura (Kyushu Univ.) ----- Break ( 15 min. ) ----- ---------------------------------------- Tue, Apr 21 PM (14:30 - 15:30) ---------------------------------------- (6) 14:30 - 15:30 [Invited Talk] Evolution and threat of botnet Toshiaki Sudou (NTT Communications) ----- Break ( 15 min. ) ----- ---------------------------------------- Tue, Apr 21 PM (15:45 - 17:00) ---------------------------------------- (7) 15:45 - 16:10 A design of testable response analyzers in built-in self-test Yuki Fukazawa, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) (8) 16:10 - 16:35 Pulse Generation Analysis for SER Estimation Targeted to Cell-based Design. Daisuke Kozuwa, Masayoshi Yoshimura, Yusuke Matsunaga (Kyusyu Univ.) (9) 16:35 - 17:00 Pulse Propagation Analysis for SER Evaluation of Logic Circuits Shoji Harada, Yusuke Akamine, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ) === Technical Committee on Dependable Computing (DC) === # FUTURE SCHEDULE: Mon, May 18, 2009 - Wed, May 20, 2009: [Mon, Mar 9] Fri, Jun 19, 2009: Kikai-Shinko-Kaikan Bldg. [Wed, Apr 15], Topics: Design, Test, Verification # SECRETARY: Masato Kitakami Graduate School of Advanced Integration Science, Chiba University 1-33 Yayoi-cho Inage-ku, Chiba 263-8522 JAPAN TEL/FAX +43.290.3039 E-mail:     f ulty  ba-u === Technical Committee on Computer Systems (CPSY) === # FUTURE SCHEDULE: Mon, May 18, 2009 - Wed, May 20, 2009: [Mon, Mar 9] # SECRETARY: Morihiro KUGA (Kumamoto Univ.) TEL +81-96-342-3647, FAX +81-96-342-3599 E-mail:    am  -u Last modified: 2009-02-20 19:28:30 |
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