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Technical Committee on VLSI Design Technologies (VLD)

Chair		Kazutoshi Kobayashi (Kyoto Inst. of Tech.)
Vice Chair		Minako Ikeda (NTT)
Secretary		Daisuke Kanemoto (Osaka Univ.), Makoto Miyamura (NEC)

Technical Committee on Hardware Security (HWS)

[schedule] [select]

Chair		Yasuhisa Shimazaki (Renesas Electronics)
Vice Chair		Makoto Nagata (Kobe Univ.), Daisuke Suzuki (Mitsubishi Electric)
Secretary		Junko Takahashi (NTT), Daisuke Fujimotoi (NAIST)

Conference Date	Mon, Mar 7, 2022 09:10 - 16:45 Tue, Mar 8, 2022 09:30 - 17:40
Topics	Design Technology for System-on-Silicon, Hardware Security, etc.
Conference Place
Registration Fee	This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on VLD, HWS.

	09:00-09:10	Opening Address ( 10 min. )
Mon, Mar 7 AM 09:10 - 10:50
(1)	09:10-09:35	Improved placement-method of standard cells considering parallel routing	Takeru Furuyashiki, Kunihiro Fujiyoshi (TUAT)
(2)	09:35-10:00	Bottleneck Channel Routing to Reduce the Area of Analog VLSI	Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Yukichi Todoroki, Makoto Minami (Jedat)
(3)	10:00-10:25	A Heuristic Scheduling Algorithm with Variable-Cycle Approximate Operations in High-Level Synthesis	Koyu Ohata, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama (Ritsumeikan Univ.)
(4)	10:25-10:50	Datapath Synthesis Considering Temperature Dependent Timing Skew	Mineo Kaneko (JAIST)
	10:50-11:00	Break ( 10 min. )
Mon, Mar 7 AM 11:00 - 12:15
(5)	11:00-11:25	Attribute-based Encryption Acceleration by Pairing Engine Hardware on FPGA	Anawin Opasatian, Makoto Ikeda (EEIS, The University of Tokyo)
(6)	11:25-11:50	Design and Measurement of Crypto Processor for Post Quantum Cryptography CRYSTALS-Kyber	Taishin Shimada, Makoto Ikeda (Univ. of Tokyo)
(7)	11:50-12:15	An efficient scheme of homomorphic encryption for stochastic computing and its performance evaluation	Ryusuke Koseki, Rei Ueno, Akira Ito, Naofumi Homma (Tohoku Univ.)
	12:15-13:15	Lunch Break ( 60 min. )
Mon, Mar 7 PM 13:15 - 14:55
(8)	13:15-13:40	[Memorial Lecture] An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers	Lingxiao Hou, Yutaka Masuda, Tohru Ishihara (Nagoya Univ.)
(9)	13:40-14:05	[Memorial Lecture] DistriHD: A Memory Efficient Distributed Binary Hyperdimensional Computing Architecture for Image Classification	Dehua Liang, Jun Shiomi, Noriyuki Miura (Osaka Univ.), Hiromitsu Awano (Kyoto Univ.)
(10)	14:05-14:30	Measurement Results of Nonvolatile Flip-Flops Using FiCC for IoT Processors with Intermittent Operations	Yuki Abe, Kazutoshi Kobayashi (KIT), Hiroyuki Ochi (Ritsumeikan Univ.)
(11)	14:30-14:55	MTJ-based non-volatile SRAM circuit with Approximate Image-data Storing for energy saving	Hisato Miyauchi, Kimiyoshi Usami (SIT)
	14:55-15:05	Break ( 10 min. )
Mon, Mar 7 PM 15:05 - 16:45
(12)	15:05-15:30	Low-Energy and Fast Inference Method for Spiking Neural Networks Using Dynamic Threshold Adjustment	Takehiro Habara, Hiromitsu Awano (Kyoto Univ.)
(13)	15:30-15:55	High-throughput In-Memory Accelerator for Binarized Neural Network based on 8T-SRAM	Hiroto Tagata, Hiromitsu Awano (Kyoto Univ.)
(14)	15:55-16:20	A Force-Haptic Guided Control System for Smooth Manipulation of Flexible Objects by Teleoperated Robots	Satoko Iida, Hiromitu Awano (Kyoto Univ.)
(15)	16:20-16:45	AmoebaSAT-based Efficient Accelerator for Autonomous Driving Application	Yusuke Inuma, Yuko Hara-Azumi (Tokyo Tech)
Tue, Mar 8 AM 09:30 - 10:45
(16)	09:30-09:55	A Study on Interface Circuits Using Click Element Between Synchronous-asynchronous Domains	Shogo Semba, Hiroshi Saito (UoA)
(17)	09:55-10:20	Wafer-Level Characteristic Variation Modeling with Considering Discontinuous Effect Caused by Manufacturing Equipment	Takuma Nagao (National Institute of Technology (KOSEN)), Michihiro Shintani (Nara Institute of Science and Technology), Ken'ichi Yamaguchi, Hiroshi Iwata (National Institute of Technology (KOSEN)), Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki (SCK), Michiko Inoue (Nara Institute of Science and Technology)
(18)	10:20-10:45	Evaluation of leakage-based LR-PUF's resistance to machine learning attacks	Tomoaki Oikawa, Kimiyoshi Usami (SIT)
	10:45-11:00	Break ( 15 min. )
Tue, Mar 8 AM 11:00 - 11:50
(19)	11:00-11:25	Evaluation of a Lightweight Cryptographic Finalist on SROS2	Shu Takemoto, Yoshiya Ikezaki, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.)
(20)	11:25-11:50	A Method for Automatic Test Pattern Generation using an SMT Solver for HDL Code	Ryoichi Isawa, Nobuyuki Kanaya, Yoshitada Fujiwara, Tatsuta Takehisa, Hayato Ushimaru, Dai Arisue, Daisuke Makita, Satoshi Mimura, Daisuke Inoue (NICT)
	11:50-13:00	Lunch Break ( 70 min. )
Tue, Mar 8 PM 13:00 - 14:40
(21)	13:00-13:25	Implementation Evaluation of Glitch PUF Using a Low-Latency Cryptography MANTIS	Kosuke Hamaguchi, Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.)
(22)	13:25-13:50	A Study on Small Area Circuits for CMOS Image Sensors with Message Authentication Codes (1) -- Drive Circuit and Pixel Array Configuration --	Yoshihiro Akamatsu, Hiroaki Ogawa, Tatsuya Oyama, Hayato Tatsuno, Yu Sekioka, Shunsuke Okura, Takeshi Fujino (Ritsumeikan Univ)
(23)	13:50-14:15	A Study on Small Area Circuits for CMOS Image Sensor with Message Authentication codes (2) -- Code generation circuit --	Yu Sekioka, Hiroaki Ogawa, Hayato Tatsuno, Tatsuya Oyama, Yoshihiro Akamatsu, Shunsuke Okura, Takeshi Fujino (Ritsumeikan Univ)
(24)	14:15-14:40	A Study on Security Evaluation of COSO-based TRNG	Ryuichi Minagawa, Kotaro Hayashi, Naoya Torii (Soka Univ)
	14:40-14:55	Break ( 15 min. )
Tue, Mar 8 PM 14:55 - 16:35
(25)	14:55-15:20	Evaluation of Side-channel Leaks Specific to Unrolled AES Hardware	Ayano Nakashima, Rei Ueno, Naofumi Homma (Tohoku Univ.)
(26)	15:20-15:45	Bypassing Isolated Execution on RISC-V Keystone using Fault Injection	Shoei Nashimoto, Daisuke Suzuki (Mitsubishi Electric), Rei Ueno, Naofumi Homma (Tohoku Univ.)
(27)	15:45-16:10	Evaluation Method for EM Information Leakage from Speakerphone Using Voice Frequency Spectrum Analysis	Hiroyuki Ueda, Seiya Takano, Daisuke Fujimoto, Yuichi Hayashi (NAIST)
(28)	16:10-16:35	Fundamental Evaluation Method for EM Information Leakage Caused by Hardware Trojans on Signal Cables -- Impact of Modulation Factor and Emission Intensity --	Taiga Yukawa, Shugo Kaji, Daisuke Fujimoto, Yuichi Hayashi (NAIST)
	16:35-16:50	Break ( 15 min. )
Tue, Mar 8 PM 16:50 - 17:40
(29)	16:50-17:15	Physical Spoofing Attack on LiDAR-based Object Detection and Its Demonstration	Yuki Fukatsu, Ryuuya Ichinose, Shinsei Ueda, Ataru Kubo, Naoki Yoshida, Tsutomu Matsumoto (Yokohama National Univ.)
(30)	17:15-17:40	Development of a Test Environment for Attack-Resistance Evaluation of Matrix Direct ToF Lidar	Masato Suzuki, Daisuke Fujimoto, Yuichi Hayashi (NAIST)

Announcement for Speakers
General Talk	Each speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD	Technical Committee on VLSI Design Technologies (VLD) [Latest Schedule]
	Contact Address	Daisuke KANEMOTO (Osaka Univ. ) E-: deeieng-u
	Announcement	See also VLD's homepage: http://www.ieice.org/~vld/
HWS	Technical Committee on Hardware Security (HWS) [Latest Schedule]
	Contact Address	Junko Takahashi(NTT) E-:hws-c